Integrated circuit design and fabrication method by way of detecting and scoring hotspots

• US 8,434,030 B1
• Filed: 01/05/2012
• Issued: 04/30/2013
• Est. Priority Date: 01/05/2012
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hou, Hsin-Ming, Kung, Ji-Fu
• Primary Examiner(s): LEVIN, NAUM B
• Application Number:
  US13/343,774
• Time in Patent Office: 481 Days
• Field of Search: 716/52, 716/54, 716/56, 716/112
• US Class Current: 716/52
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

An integrated circuit design and fabrication method includes the following steps. Firstly, an integrated circuit design layout is provided. Then, a first hotspot group and a second hotpot group are searched from the integrated circuit design layout. Then, a hotspot score is acquired according to the first hotspot group, the second hotpot group and a product functionality. If the hotspot score is higher than a criterion, the integrated circuit design layout is corrected according to the first hotspot group and the second hotpot group.

Claims

1. An integrated circuit design and fabrication method, comprising steps of:

providing an integrated circuit design layout;

searching a first hotspot group and a second hotspot group from the integrated circuit design layout by analyzing routing indices and statistical indices, wherein the first hotspot group includes hotspots from systematic defects, and the second hotspot group includes hotspots from random defects;

acquiring a hotspot score by using a computer according to the first hotspot group, the second hotspot group and a product functionality; and

if the hotspot score is higher than a criterion, correcting the integrated circuit design layout according to the first hotspot group and the second hotspot group.

2. The integrated circuit design and fabrication method according to claim 1, wherein the step of analyzing routing indices and statistical indices is respectively performed with a 3-dimensional multi-level interconnection electrical model and a random defect integral value.

3. The integrated circuit design and fabrication method according to claim 1, further comprising steps of:

searching a third hotspot group from the integrated circuit design layout, wherein the third hotspot group includes hotspots from parametric defects; and

acquiring the hotspot score according to the first hotspot group, the second hotspot group, the third hotspot group and the product functionality.

4. The integrated circuit design and fabrication method according to claim 1, further comprising steps of:

searching a fourth hotspot group from the integrated circuit design layout, wherein the fourth hotspot group includes hotspots from process tool unit sensitivity; and

acquiring the hotspot score according to the first hotspot group, the second hotspot group, the fourth hotspot group and the product functionality.

5. The integrated circuit design and fabrication method according to claim 1, further comprising steps of:

searching a third hotspot group and a fourth hotspot group from the integrated circuit design layout, wherein the third hotspot group includes hotspots from parametric defects, and the fourth hotspot group includes hotspots from process tool unit sensitivity; and

acquiring the hotspot score according to the first hotspot group, the second hotspot group, the third hotspot group, the fourth hotspot group and the product functionality.

6. The integrated circuit design and fabrication method according to claim 1, wherein the product functionality is a speed-oriented product functionality or a power-oriented product functionality.

7. The integrated circuit design and fabrication method according to claim 6, wherein the step of acquiring the hotspot score according to the first hotspot group, the second hotspot group and the product functionality includes sub-steps of:

weighted-scoring the first hotspot group according to the product functionality, so that a first group score corresponding to the first hotspot group is acquired;

weighted-scoring the second hotspot group according to the product functionality, so that a second group score corresponding to the second hotspot group is acquired; and

calculating a total of the first group score and the second group score, thereby acquiring the hotspot score.

8. The integrated circuit design and fabrication method according to claim 1, wherein the step of correcting the integrated circuit design layout according to the first hotspot group and the second hotspot group is performed by performing an optical proximity correction on a photomask pattern corresponding to the integrated circuit design layout.

9. The integrated circuit design and fabrication method according to claim 1, wherein the step of correcting the integrated circuit design layout according to the first hotspot group and the second hotspot group is performed by performing a metal slot and dummy fill technology.

10. The integrated circuit design and fabrication method according to claim 1, wherein if the hotspot score is lower than a criterion, the integrated circuit design and fabrication method further comprises an in-line real silicon wafer verification step.

11. The integrated circuit design and fabrication method according to claim 10, wherein the in-line real silicon wafer verification step comprises sub-steps:

extracting hard fail defect patterns; and

searching a circuit layout pattern corresponding to the hotspots from a real silicon wafer layout according to the hard fail defect patterns, and correcting the circuit layout pattern.

12. The integrated circuit design and fabrication method according to claim 10, wherein the in-line real silicon wafer verification step comprises sub-steps:

extracting soft fail electrical data; and

searching a circuit layout pattern corresponding to the hotspots from a real silicon wafer layout according to the soft fail electrical data, and correcting the circuit layout pattern.

13. The integrated circuit design and fabrication method according to claim 10, further comprising steps:

sending uncorrected hotspots into a hotspot library, and classifying the uncorrected hotspots according to defect types; and

allowing a circuit layout corresponding to the hotspots of the hotspot library to be fed back to a circuit layout designer.