Multi-level clock gating circuitry transformation

• US 8,434,047 B1
• Filed: 01/25/2011
• Issued: 04/30/2013
• Est. Priority Date: 05/29/2007
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Jiang, Yunjian (William), Srinivasan, Arvind, Banerjee, Joy, Li, Yinghua, Das, Partha, Chaudhuri, Samit
• Primary Examiner(s): Levin, Naum
• Application Number:
  US13/013,024
• Time in Patent Office: 826 Days
• Field of Search: 716/109, 716/132, 716/133
• US Class Current: 716/133
• CPC Class Codes: G06F 2111/06 Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]
• CPC Class Codes: G06F 2117/04 Clock gating
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/396 Clock trees

Abstract

A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.

Claims

1. A computer-implemented method of optimizing circuitry in an integrated circuit (IC) design, the method comprising:

determining, with one or more processors associated with one or more computer systems, a plurality of signals which feed into enable inputs of a plurality of clock gates, the clock gates gating a plurality of sequential elements in the IC design;

identifying, with the one or more processors associated with the one or more computer systems, combinational logic which is shared among the plurality of signals; and

transforming, with the one or more processors associated with the one or more computer systems, the plurality of clock gates into multiple levels of clock-gating circuitry based on the shared combinational logic.

2. The method of claim 1, wherein a first level of the multiple levels of clock-gating circuitry includes a first clock gate and an enable input of the first clock gate is driven by the shared combinational logic.

3. The method of claim 1, wherein a first level of the multiple levels of clock-gating circuitry includes a first clock gate and an enable input of the first clock gate is driven by the shared combinational logic, and wherein a second level of the multiple levels of clock-gating circuitry includes a plurality of secondary clock gates and a clock input of each of the secondary clock gates is driven by an output signal of the first clock gate, and an enable input of each of the secondary clock gates is driven by non-shared combinational logic.

4. The method of claim 1, wherein identifying, with the one or more processors associated with the one or more computer systems, combinational logic which is shared among the plurality of signals comprises analyzing a fan-in cone of each of the sequential elements in the IC design.

5. The method of claim 1, whereby the transformed clock-gated circuitry reduces the area and power consumed by the IC design.

6. The method of claim 1, wherein the clock gates include flexible clock gates.

7. The method of claim 1, wherein the clock gates include inflexible clock gates.

8. A computer program product stored on a non-transitory computer-readable medium for optimizing circuitry in an integrated circuit (IC) design, the computer program product comprising:

code for determining a plurality of signals which feed into enable inputs of a plurality of clock gates, the clock gates gating a plurality of sequential elements in the IC design;

code for identifying combinational logic which is shared among the plurality of signals; and

code for transforming the plurality of clock gates into multiple levels of clock-gating circuitry based on the shared combinational logic.

9. The computer program product of claim 8, wherein a first level of the multiple levels of clock-gating circuitry includes a first clock gate and an enable input of the first clock gate is driven by the shared combinational logic.

10. The computer program product of claim 8, wherein a first level of the multiple levels of clock-gating circuitry includes a first clock gate and an enable input of the first clock gate is driven by the shared combinational logic, and wherein a second level of the multiple levels of clock-gating circuitry includes a plurality of secondary clock gates and a clock input of each of the secondary clock gates is driven by an output signal of the first clock gate, and an enable input of each of the secondary clock gates is driven by non-shared combinational logic.

11. The computer program product of claim 8, wherein the code for identifying combinational logic which is shared among the plurality of signals comprises code for analyzing a fan-in cone of each of the sequential elements in the IC design.

12. The computer program product of claim 8, whereby the transformed clock-gated circuitry reduces the area and power consumed by the IC design.

13. The computer program product of claim 8, wherein the clock gates include flexible clock gates.

14. A system for optimizing clock-gated circuitry in an integrated circuit (IC) design, the system comprising:

one or more processors; and

a memory coupled to the one or more processors, the memory configured to store a plurality of code modules which when executed by the processor cause the processor to;

determine a plurality of signals which feed into enable inputs of a plurality of clock gates, the clock gates gating a plurality of sequential elements in the IC design;

identify combinational logic which is shared among the plurality of signals; and

transform the plurality of clock gates into multiple levels of clock-gating circuitry based on the shared combinational logic.

15. The system of claim 14, wherein a first level of the multiple levels of clock-gating circuitry includes a first clock gate and an enable input of the first clock gate is driven by the shared combinational logic.

16. The system of claim 14, wherein a first level of the multiple levels of clock-gating circuitry includes a first clock gate and an enable input of the first clock gate is driven by the shared combinational logic, and wherein a second level of the multiple levels of clock-gating circuitry includes a plurality of secondary clock gates and a clock input of each of the secondary clock gates is driven by an output signal of the first clock gate, and an enable input of each of the secondary clock gates is driven by non-shared combinational logic.

17. The system of claim 14, wherein to identify combinational logic which is shared among the plurality of signals the one or more processors are configured to analyze a fan-in cone of each of the sequential elements in the IC design.

18. The system of claim 14, whereby the transformed clock-gated circuitry reduces the area and power consumed by the IC design.

19. The system of claim 14, wherein the clock gates include flexible clock gates.

20. The system of claim 14, wherein the clock gates include inflexible clock gates.