Treatment of gate dielectric for making high performance metal oxide and metal oxynitride thin film transistors

• US 8,435,843 B2
• Filed: 01/20/2012
• Issued: 05/07/2013
• Est. Priority Date: 07/02/2008
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Ye, Yan
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US13/355,316
• Publication Number:
  US 20120112186A1
• Time in Patent Office: 473 Days
• Field of Search: 257/59, 257/72, 257/359, 257/40, 257/43, 257/E29.296, 438/104, 438/158
• US Class Current: 438/158
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Embodiments of the present invention generally include TFTs and methods for their manufacture. The gate dielectric layer in the TFT may affect the threshold voltage of the TFT. By treating the gate dielectric layer prior to depositing the active channel material, the threshold voltage may be improved. One method of treating the gate dielectric involves exposing the gate dielectric layer to N₂O gas. Another method of treating the gate dielectric involves exposing the gate dielectric layer to N₂O plasma. Silicon oxide, while not practical as a gate dielectric for silicon based TFTs, may also improve the threshold voltage when used in metal oxide TFTs. By treating the gate dielectric and/or using silicon oxide, the threshold voltage of TFTs may be improved.

Claims

1. A thin film transistor fabrication method, comprising:

depositing a gate dielectric layer over a gate electrode and a substrate;

exposing the gate dielectric layer to an oxygen containing plasma;

sputter depositing a semiconductor layer over the gate dielectric layer, the semiconductor layer comprising oxygen, zinc, gallium, and indium;

depositing a conductive layer over the semiconductor layer; and

etching the conductive layer to define source and drain electrodes and an active channel, the active channel exposing a portion of the semiconductor layer.

2. The method of claim 1, wherein the gate dielectric layer comprises silicon nitride, silicon oxide, or a bi-layer of silicon nitride and silicon oxide.

3. The method of claim 1, further comprising exposing the gate dielectric layer to a hydrogen plasma after exposing the gate dielectric to the oxygen containing plasma.

4. The method of claim 1, wherein the semiconductor layer further comprises nitrogen.

5. The method of claim 1, wherein the exposing is performed in-situ with the gate dielectric layer deposition.

6. The method of claim 1, wherein the oxygen containing plasma comprises N₂O.

7. A thin film transistor fabrication method, comprising:

depositing a silicon nitride layer over a gate electrode and a substrate;

depositing a silicon oxide layer over the silicon nitride layer;

sputter depositing a semiconductor layer over the silicon oxide layer, the semiconductor layer comprising oxygen, zinc, gallium and indium;

depositing a conductive layer over the semiconductor layer; and

etching the conductive layer to define source and drain electrodes and an active channel, the active channel exposing a portion of the semiconductor layer.

8. The method of claim 7, further comprising exposing the silicon oxide layer to N₂O plasma.

9. The method of claim 8, further comprising exposing the silicon oxide layer to hydrogen plasma after exposing the silicon oxide layer to N₂O plasma.

10. The method of claim 8, wherein the exposing occurs in situ with the silicon oxide layer deposition.

11. The method of claim 8, further comprising exposing the silicon oxide layer to oxygen plasma after the exposing to N₂O plasma.

12. The method of claim 7, wherein the semiconductor layer further comprises nitrogen.

13. A thin film transistor fabrication method, comprising:

depositing a silicon oxide layer over a gate electrode and a substrate;

sputter depositing a semiconductor layer over the silicon oxide layer, the semiconductor layer comprising oxygen, zinc, gallium and indium;

depositing a conductive layer over the semiconductor layer; and

etching the conductive layer to define source and drain electrodes and an active channel, the active channel exposing a portion of the semiconductor layer.

14. The method of claim 13, further comprising exposing the silicon oxide layer to N₂O plasma.

15. The method of claim 14, further comprising exposing the silicon oxide layer to hydrogen plasma after exposing the silicon oxide layer to N₂O plasma.

16. The method of claim 14, wherein the exposing occurs in situ with the silicon oxide layer deposition.

17. The method of claim 14, further comprising exposing the silicon oxide layer to oxygen plasma after the exposing to N₂O plasma.

18. The method of claim 13, wherein the semiconductor layer further comprises nitrogen.

19. A thin film transistor, comprising:

a silicon oxide layer disposed over a gate electrode and a substrate;

a semiconductor layer disposed over the silicon oxide layer, the semiconductor layer comprising oxygen, zinc, gallium and indium; and

a source electrode and a drain electrode disposed over the semiconductor layer, the source and drain electrodes spaced from each other to expose a portion of the semiconductor layer.

20. The transistor of claim 19, further comprising a silicon nitride layer disposed on the gate electrode and substrate, and below the silicon oxide layer.