Trench type semiconductor device and fabrication method for the same

• US 8,435,860 B2
• Filed: 04/30/2012
• Issued: 05/07/2013
• Est. Priority Date: 07/29/2008
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Yoshimochi, Kenichi
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US13/459,407
• Publication Number:
  US 20120276728A1
• Time in Patent Office: 372 Days
• Field of Search: 438/270, 438/271, 438/272, 438/273, 438/274, 257/E21.585
• US Class Current: 438/272
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A fabrication method for a trench type semiconductor device includes: forming a first base layer; forming a gate insulating film on a bottom and sidewall surfaces of a trench; forming a gate electrode for filling up into the trench; covering the gate electrode and forming an interlayer insulating film; forming a second base layer on the first base layer; forming a first main electrode layer on the second base layer; forming a first main electrode which passes through the first main electrode layer by applying the interlayer insulating film as a mask, is connected to the second base layer in the bottom surface of a self-aligned contact trench, and is connected to the first main electrode layer of the self-aligned contact trench; forming a second main electrode layer at a back side of the first base layer; and forming a second main electrode at the second main electrode layer.

Claims

1. A fabrication method for a trench type semiconductor device comprising:

forming a first base layer of a first conductivity type with high resistivity;

forming a gate insulating film on a bottom surface and a sidewall surface of a trench formed from a surface of the first base layer;

forming the gate electrode for filling up into the trench on the gate insulating film;

forming an impurity layer on an upper part of the gate electrode;

forming an interlayer insulating film so as to cover the gate electrode;

forming a second base layer of a second conductivity type on the surface of the first base layer formed more shallowly than the bottom surface of the trench;

forming a first main electrode layer of the first conductivity type on a surface of the second base layer;

forming a first main electrode which passes through the first main electrode layer by applying the interlayer insulating film as a mask, is connected to the second base layer in the bottom surface of a self-aligned contact trench formed in the second base layer, and is connected to the first main electrode layer in a sidewall surface of the self-aligned contact trench;

forming a second main electrode layer at a back side of the first base layer; and

forming a second main electrode at the second main electrode layer.

2. The fabrication method for a trench type semiconductor device according to claim 1, wherein

the interlayer insulating film is formed with a LOCOS oxidation film, and is formed by covering a part of the gate insulating film and a part of the first main electrode layer.

3. The fabrication method for a trench type semiconductor device according to claim 1, wherein

the first main electrode is formed all over a device surface in forming the first main electrode.

4. The fabrication method for a trench type semiconductor device according to claim 1, wherein

the step of forming the first main electrode includes the step of forming a barrier metal layer on the underlying of the first main electrode.

5. The fabrication method for a trench type semiconductor device according to claim 1, wherein

both the first base layer and the 2nd base layer have the surface orientation of (100) in forming the first base layer and forming the second base layer.

6. The fabrication method for a trench type semiconductor device according to claim 1, wherein

the trench has a rectangular plane pattern structure in forming the trench.

7. The fabrication method for a trench type semiconductor device according to claim 1, wherein

both the bottom surface and the sidewall surface of the trench have the surface orientation of (100) in forming the trench.

8. The fabrication method for a trench type semiconductor device according to claim 1, wherein

both the bottom surface and the sidewall surface of the self-aligned contact trench have the surface orientation of (100) in forming the self-aligned contact trench.

9. The fabrication method for a trench type semiconductor device according to claim 1, wherein

the self-aligned contact trench has a lattice-like pattern in forming the self-aligned contact trench.

10. The fabrication method for a trench type semiconductor device according to claim 1, wherein

the self-aligned contact trench has a zigzagged lattice-like pattern in forming the self-aligned contact trench.

11. The fabrication method for a trench type semiconductor device according to claim 1, wherein

the self-aligned contact trench has a stripe shaped pattern.

12. The fabrication method for a trench type semiconductor device according to claim 1, wherein the impurity layer formed on the upper part of the gate electrode is implanted with a dosage amount from 5×

10¹⁵ atoms/cm² to 5×

10¹⁶ atoms/cm², and is implanted with an accelerating voltage from 5 keV to 40 keV.

13. The fabrication method for a trench type semiconductor device according to claim 1, wherein a high impurity concentration of the impurity layer formed on the upper part of the gate electrode is larger than high impurity concentrations of the second base layer and the first main electrode layer.