Post passivation interconnection schemes on top of IC chips
First Claim
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1. A method for fabricating a chip, comprising:
- providing a silicon substrate and an interconnecting structure over said silicon substrate, wherein said interconnecting structure is formed by a process comprising a damascene process, an electroplating process and a CMP process; and
forming a power bus over said silicon substrate, wherein said forming said power bus comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer.
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Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
201 Citations
30 Claims
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1. A method for fabricating a chip, comprising:
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providing a silicon substrate and an interconnecting structure over said silicon substrate, wherein said interconnecting structure is formed by a process comprising a damascene process, an electroplating process and a CMP process; and forming a power bus over said silicon substrate, wherein said forming said power bus comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for fabricating a chip, comprising:
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providing a silicon substrate, a first internal circuit in or on said silicon substrate, a second internal circuit in or on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit, and a passivation layer over said dielectric layer; and forming a power bus and a polymer layer over said passivation layer, wherein said polymer layer comprises a portion over said power bus, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said power bus and said second interconnecting structure, wherein said forming said power bus comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method for fabricating a chip, comprising:
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providing a silicon substrate, a dielectric layer over said silicon substrate, an interconnecting structure over said silicon substrate and in said dielectric layer, and a separating layer over said dielectric layer, wherein said interconnecting structure is formed by a process comprising a damascene process, an electroplating process and a CMP process, wherein said separating layer comprises an oxide layer; and forming an interconnect line over said separating layer, wherein said interconnect line is connected to said interconnecting structure through a via in said separating layer, wherein said forming said interconnect line comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer. - View Dependent Claims (18, 19, 20, 21, 22, 23)
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24. A method for fabricating a chip, comprising:
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providing a silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first and second interconnecting structures are formed by a process comprising a damascene process, an electroplating process and a CMP process, and a separating layer over said dielectric layer, wherein said separating layer comprises a nitride; and forming a power interconnect and a polymer layer over said separating layer, wherein said polymer layer has a portion over said power interconnect, wherein said first interconnecting structure is connected to said second interconnecting structure through said power interconnect, wherein said forming said power interconnect comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer. - View Dependent Claims (25, 26, 27)
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28. A method for fabricating a chip, comprising:
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providing a silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is formed by a process comprising a damascene process, an electroplating process and a CMP process, a second interconnecting structure over said silicon substrate and in said dielectric layer, and a separating layer over said dielectric layer; and forming a signal interconnect over said separating layer, wherein said first interconnecting structure is connected to said second interconnecting structure through said signal interconnect, wherein a top surface of said signal interconnect has no access for external connection, wherein said forming said signal interconnect comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer. - View Dependent Claims (29, 30)
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Specification