Multi-layer via-less thin film resistor
First Claim
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1. A device, comprising:
- an integrated circuit die, the integrated circuit die including;
a semiconductor substrate;
a first interconnect having a first conductor layer on the substrate and a second conductor layer on the first conductor, the first interconnect having a first sidewall transverse to the substrate;
a second interconnect spaced from the first interconnect, the second interconnect having the first conductor layer on the substrate and the second conductor layer on the first conductor layer, the second interconnect having a second sidewall transverse to the substrate; and
a resistive element having a plurality of resistive layers formed on the substrate between the first and second interconnects and on the first and second sidewalls of the first and second interconnects, the plurality of resistive layers comprising;
a first resistor layer of chromium boride having a first temperature coefficient of resistance and electrically connecting the first conductor layers of the first and second interconnects; and
a second resistor layer of chromium boride on the first resistor layer, the second resistor layer having a second temperature coefficient of resistance different from the first temperature coefficient of resistance.
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Abstract
The present disclosure is directed to a thin film resistor having a first resistor layer having a first temperature coefficient of resistance and a second resistor layer on the first resistor layer, the second resistor layer having a second temperature coefficient of resistance different from the first temperature coefficient of resistance. The first temperature coefficient of resistance may be positive while the second temperature coefficient of resistance is negative. The first resistor layer may have a thickness in the range of 50 and 150 angstroms and the second resistor layer may have a thickness in the range of 20 and 50 angstroms.
62 Citations
17 Claims
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1. A device, comprising:
an integrated circuit die, the integrated circuit die including; a semiconductor substrate; a first interconnect having a first conductor layer on the substrate and a second conductor layer on the first conductor, the first interconnect having a first sidewall transverse to the substrate; a second interconnect spaced from the first interconnect, the second interconnect having the first conductor layer on the substrate and the second conductor layer on the first conductor layer, the second interconnect having a second sidewall transverse to the substrate; and a resistive element having a plurality of resistive layers formed on the substrate between the first and second interconnects and on the first and second sidewalls of the first and second interconnects, the plurality of resistive layers comprising; a first resistor layer of chromium boride having a first temperature coefficient of resistance and electrically connecting the first conductor layers of the first and second interconnects; and a second resistor layer of chromium boride on the first resistor layer, the second resistor layer having a second temperature coefficient of resistance different from the first temperature coefficient of resistance. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of forming an integrated circuit die, comprising:
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forming a first interconnect on a substrate, the first interconnect having a first conductor layer on the substrate, a second conductor layer on the first conductor, and a first sidewall transverse to the substrate; forming a second interconnect on the substrate spaced from the first interconnect, the second interconnect having the first conductor layer on the substrate and the second conductor layer on the first conductor layer, the second interconnect having a second sidewall transverse to the substrate; and forming a thin film resistor on the substrate between the first and second interconnects and on the first and second sidewalls of the first and second interconnects, the forming comprising; forming a first resistor layer on the substrate electrically connecting the first conductor layers of the first and second interconnects, the first resistor layer having a first composition of chromium boride; and forming a second resistor layer on the first resistor layer, the second resistor layer having a second composition of chromium boride, wherein the thin film resistor is thinner than the first and second interconnects. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A device, comprising:
an integrated circuit die, the integrated circuit die including; a semiconductor substrate; a first interconnect having a first conductor layer on the substrate and a second conductor layer on the first conductor, the first interconnect having a first sidewall transverse to the substrate; a second interconnect spaced from the first interconnect, the second interconnect having the first conductor layer on the substrate and the second conductor layer on the first conductor layer, the second interconnect having a second sidewall transverse to the substrate; and a resistive element having a plurality of resistive layers formed on the substrate between the first and second interconnects and on the first and second sidewalls of the first and second interconnects, the plurality of resistive layers comprising; a first resistive layer electrically connecting the first conductor layers of the first and second interconnects; and a second resistive layer formed on the first resistive layer, wherein the resistive element is thinner than the first and second interconnects. - View Dependent Claims (15, 16, 17)
Specification