Semiconductor memory device and semiconductor device

• US 8,437,165 B2
• Filed: 02/25/2011
• Issued: 05/07/2013
• Est. Priority Date: 03/04/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi, Takemura, Yasuhiko
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): HUERTA, PABLO S
• Application Number:
  US13/034,750
• Publication Number:
  US 20110216571A1
• Time in Patent Office: 802 Days
• Field of Search: 365/72
• US Class Current: 365/72
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A matrix is formed using a plurality of memory cells in each of which a drain of the writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor. A gate of the writing transistor, a source of the writing transistor, a source of the reading transistor, and a drain of the reading transistor are connected to a writing word line, a writing bit line, a reading bit line, and a bias line, respectively. In order to reduce the number of wirings, a writing word line to which the gate of the writing transistor is not connected is substituted for the reading word line. Further, the writing bit line is substituted for the reading bit line.

Claims

1. A semiconductor memory device comprising:

a first memory cell including a first transistor, a second transistor, and a capacitor;

a second memory cell including a third transistor;

a first line;

a second line;

a third line;

a fourth line; and

a fifth line,

wherein a gate of the first transistor is electrically connected to the first line,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and a first electrode of the capacitor,

wherein a second electrode of the capacitor and a gate of the third transistor are electrically connected to the second line,

wherein the other of the source and the drain of the first transistor is electrically connected to the third line,

wherein one of a source and a drain of the second transistor is electrically connected to the fourth line, and

wherein the other of the source and the drain of the second transistor is electrically connected to the fifth line.

2. The semiconductor memory device according to claim 1,

wherein the first line and the second line are parallel to each other, and

wherein the third line, the fourth line, and the fifth line are parallel to each other.

3. The semiconductor memory device according to claim 1,

wherein the first line and the third line are orthogonal to each other.

4. The semiconductor memory device according to claim 1,

wherein one of a source and a drain of the third transistor is electrically connected to the third line.

5. The semiconductor memory device according to claim 1,

wherein at least one of the first transistor, the second transistor, and the third transistor includes an oxide semiconductor.

6. The semiconductor memory device according to claim 1,

wherein, when the third line is supplied with a first potential, the fourth line is supplied with a second potential which is substantially the same potential as the first potential.

7. A semiconductor device including the semiconductor memory device according to claim 1.

8. A semiconductor memory device comprising:

a first memory cell including a first transistor, a second transistor, and a capacitor;

a second memory cell including a third transistor;

a first line;

a second line;

a third line; and

a fourth line,

wherein a gate of the first transistor is electrically connected to the first line,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and a first electrode of the capacitor,

wherein a second electrode of the capacitor and a gate of the third transistor are electrically connected to the second line,

wherein the other of the source and the drain of the first transistor is electrically connected to the third line,

wherein one of a source and a drain of the second transistor is electrically connected to the fourth line, and

wherein the other of the source and the drain of the second transistor is electrically connected to the third line.

9. The semiconductor memory device according to claim 8,

wherein the first line and the second line are parallel to each other, and

wherein the third line and the fourth line are parallel to each other.

10. The semiconductor memory device according to claim 8,

wherein the first line and the third line are orthogonal to each other.

11. The semiconductor memory device according to claim 8,

wherein one of a source and a drain of the third transistor is electrically connected to the third line.

12. The semiconductor memory device according to claim 8,

wherein at least one of the first transistor, the second transistor, and the third transistor includes an oxide semiconductor.

13. The semiconductor memory device according to claim 8,

wherein, when the third line is supplied with a first potential, the fourth line is supplied with a second potential which is substantially the same potential as the first potential.

14. A semiconductor device including the semiconductor memory device according to claim 8.

15. A semiconductor memory device comprising:

a first memory cell including a first transistor, a second transistor, and a first capacitor;

a second memory cell including a third transistor;

a third memory cell including a fourth transistor, a fifth transistor, and a second capacitor;

a first line;

a second line;

a third line; and

a fourth line,

wherein a gate of the first transistor and a gate of the fourth transistor are electrically connected to the first line,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and a first electrode of the first capacitor,

wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the fifth transistor and a first electrode of the second capacitor,

wherein a second electrode of the first capacitor, a second electrode of the second capacitor, and a gate of the third transistor are electrically connected to the second line,

wherein the other of the source and the drain of the first transistor is electrically connected to the third line,

wherein one of a source and a drain of the second transistor and one of a source and a drain of the fifth transistor are electrically connected to the fourth line, and

wherein the other of the source and the drain of the second transistor is electrically connected to the third line.

16. The semiconductor memory device according to claim 15,

wherein the first line and the second line are parallel to each other, and

wherein the third line and the fourth line are parallel to each other.

17. The semiconductor memory device according to claim 15,

wherein the first line and the third line are orthogonal to each other.

18. The semiconductor memory device according to claim 15,

wherein one of a source and a drain of the third transistor is electrically connected to the third line.

19. The semiconductor memory device according to claim 15,

wherein at least one of the first transistor, the second transistor, and the third transistor includes an oxide semiconductor.

20. The semiconductor memory device according to claim 15,

wherein, when the third line is supplied with a first potential, the fourth line is supplied with a second potential which is substantially the same potential as the first potential.

21. A semiconductor device including the semiconductor memory device according to claim 15.