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Non-volatile memory with both single and multiple level cells

  • US 8,437,186 B2
  • Filed: 06/12/2012
  • Issued: 05/07/2013
  • Est. Priority Date: 08/21/2006
  • Status: Active Grant
First Claim
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1. A memory array, comprising:

  • a number of single level non-volatile memory cells;

    a number of multiple level non-volatile memory cells;

    a number of select gates coupled in series to the number of single level non-volatile memory cells and the number of multiple level non-volatile memory cells;

    wherein a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell that is directly coupled to a continuous number of additional multiple level non-volatile memory cells;

    wherein a second select gate is coupled in series to an opposite end of a number of multiple level non-volatile memory cells relative to the first select gate; and

    wherein a second single level non-volatile memory cell is interposed between and coupled to the second select gate and a second multiple level non-volatile memory cell, wherein the second single level non-volatile memory cell has a programmed voltage that is intermediate between a higher programmed voltage for the upper page of the second multiple level non-volatile memory cell and a lower resting voltage of the second select gate.

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