Non-volatile memory with both single and multiple level cells

• US 8,437,186 B2
• Filed: 06/12/2012
• Issued: 05/07/2013
• Est. Priority Date: 08/21/2006
• Status: Active Grant

• Current Assignee: Polaran
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US13/494,525
• Publication Number:
  US 20120257451A1
• Time in Patent Office: 329 Days
• Field of Search: 365/185.03, 365/185.24
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of memory cells operated as single level memory cells and a number of memory cells operated as multiple level memory cells, where a first select gate is directly coupled to a first memory cell operated as a single level memory cell interposed between and coupled to the first select gate and a continuous number of memory cells operated as multiple level memory cells.

Claims

1. A memory array, comprising:

a number of single level non-volatile memory cells;

a number of multiple level non-volatile memory cells;

a number of select gates coupled in series to the number of single level non-volatile memory cells and the number of multiple level non-volatile memory cells;

wherein a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell that is directly coupled to a continuous number of additional multiple level non-volatile memory cells;

wherein a second select gate is coupled in series to an opposite end of a number of multiple level non-volatile memory cells relative to the first select gate; and

wherein a second single level non-volatile memory cell is interposed between and coupled to the second select gate and a second multiple level non-volatile memory cell, wherein the second single level non-volatile memory cell has a programmed voltage that is intermediate between a higher programmed voltage for the upper page of the second multiple level non-volatile memory cell and a lower resting voltage of the second select gate.

2. The array of claim 1, wherein the multiple level non-volatile memory cells are comprised of a lower page and at least one upper page of data and the single level non-volatile memory cells are comprised of a single page of data.

3. The array of claim 2, wherein the first single level non-volatile memory cell has a programmed voltage that is intermediate between a higher programmed voltage for the upper page of the first multiple level non-volatile memory cell and a lower resting voltage of the first select gate.

4. The array of claim 2, wherein each page enables two data input selections.

5. The array of claim 1, wherein the array includes a number of single level memory cells and a number of multiple level non-volatile memory cells coupled in series.

6. The array of claim 1, wherein the array includes a NAND string.

7. The array of claim 6, wherein the NAND string enables 128 data input selections.

8. The array of claim 7, wherein the 128 data input selections are enabled by a continuous series of 31 multiple level non-volatile memory cells coupled to a first single level non-volatile memory cell that is coupled to a source select gate, and a second single level non-volatile memory cell that is coupled to a drain select gate.

9. The array of claim 1, wherein the array includes a number of source select gates and a number of drain select gates, and wherein no source select gate and no drain select gate are adjacent a multiple level non-volatile memory cell in a respective NAND string.

10. The array of claim 1, wherein each of the number of select gates is adjacent a single level non-volatile memory cell in a respective NAND string.

11. The array of claim 1, wherein no multiple level non-volatile memory cell is adjacent to more than one single level non-volatile memory cell in a respective NAND string.

12. A memory device, comprising:

an array of non-volatile memory cells including a string of non-volatile memory cells;

circuitry for control and access to the array of non-volatile memory cells;

wherein the array of non-volatile memory cells includes;

a number of single level non-volatile memory cells;

a number of multiple level non-volatile memory cells;

a number of select gates coupled in series to the number of single level non-volatile memory cells and the number of multiple level non-volatile memory cells;

wherein a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell that is directly coupled to a continuous number of additional multiple level non-volatile memory cells;

wherein a second select gate is coupled in series to an opposite end of a number of multiple level non-volatile memory cells relative to the first select gate; and

wherein a second single level non-volatile memory cell is interposed between and coupled to the second select gate and a second multiple level non-volatile memory cell, wherein the second single level non-volatile memory cell has a programmed voltage that is intermediate between a higher programmed voltage for the upper page of the second multiple level non-volatile memory cell and a lower resting voltage of the second select gate.

13. The memory device of claim 12, wherein the first single level non-volatile memory cell has a programmed voltage that is intermediate between a higher programmed voltage for an upper page of the first multiple level non-volatile memory cell and a lower resting voltage of the first select gate.

14. The memory device of claim 12, wherein the device includes a number of source select gates and a number of drain select gates, and wherein no source select gate and no drain select gate are adjacent one of the number of multiple level non-volatile memory cells in a respective NAND string.

15. The memory device of claim 12, wherein each of the number of select gates is adjacent one of the number of single level non-volatile memory cells in a respective NAND string.

16. The memory device of claim 12, wherein none of the number of multiple level non-volatile memory cells is adjacent to more than one of the number of single level non-volatile memory cells in a respective NAND string.

17. The memory device of claim 12, wherein the array includes a NAND string that enables 128 data input selections.

18. A method of forming a memory block, comprising:

adding a number of word lines to a string having a number of single level non-volatile memory cells and a number of multiple level memory cells for maintaining a previous memory block size;

wherein adding the number of word lines includes adding a number of non-volatile memory cells selected from single level non-volatile memory cells and multiple level memory cells; and

wherein maintaining the previous memory block size includes maintaining a particular number selected from data input selection choices, memory bits, and pages associated with the previous memory block size.

19. The method of claim 18, wherein maintaining the previous memory block size includes maintaining the number of data input selection choices on a string at around 128, the number of memory bits on a string at around 64, and the number of pages in a memory block at around 128.

20. The method of claim 19, wherein maintaining the around 128 data input selections maintaining a continuous series of 31 multiple level non-volatile memory cells coupled to a first single level non-volatile memory cell that is coupled to a source select gate and maintaining a second single level non-volatile memory cell that is coupled to a drain select gate.