Signal processing apparatus, signal transmitting system, and signal processing method
First Claim
Patent Images
1. A signal processing apparatus executing a decoding process for a digital signal Manchester-encoded by assigning two bits of “
- 10”
to any one of binary digital signals “
0 and “
1”
, and assigning two bits of “
01”
to the other binary digital signal, comprising;
a decoding unit executing the decoding process with a processing unit corresponding to a term of two bits of the Manchester-encoded digital signal so as to detect only any one of a first bit and a second bit of the Manchester-encoded digital signal,wherein the decoding unit detects only the second bit of the Manchester-encoded digital signal at a falling edge or a rising edge of a clock switched by the first bit and the second bit of the Manchester-encoded digital signal.
3 Assignments
0 Petitions
Accused Products
Abstract
A signal processing apparatus, which executing a decoding process for a digital signal Manchester-encoded by assigning two bits of “10” to any one of binary digital signals “0 and “1”, and assigning two bits of “01” to the other binary digital signal, is provide with a decoding unit which executes the decoding process with a processing unit corresponding to a term of two bits of the Manchester-encoded digital signal so as to detect only any one of the first bit and the second bit of the Manchester-encoded digital signal.
-
Citations
17 Claims
-
1. A signal processing apparatus executing a decoding process for a digital signal Manchester-encoded by assigning two bits of “
- 10”
to any one of binary digital signals “
0 and “
1”
, and assigning two bits of “
01”
to the other binary digital signal, comprising;a decoding unit executing the decoding process with a processing unit corresponding to a term of two bits of the Manchester-encoded digital signal so as to detect only any one of a first bit and a second bit of the Manchester-encoded digital signal, wherein the decoding unit detects only the second bit of the Manchester-encoded digital signal at a falling edge or a rising edge of a clock switched by the first bit and the second bit of the Manchester-encoded digital signal. - View Dependent Claims (2, 3)
- 10”
-
4. A signal processing apparatus executing a decoding process for a digital signal Manchester-encoded by assigning two bits of “
- 10”
to any one of binary digital signals “
0 and “
1”
, and assigning two bits of “
01”
to the other binary digital signal, comprising;a decoding unit executing the decoding process with a processing unit corresponding to a term of two bits of the Manchester-encoded digital signal so as to detect only any one of a first bit and a second bit of the Manchester-encoded digital signal, wherein the decoding unit executes the decoding process for the Manchester-encoded digital signal by using only a circuit element operating as substantially phase-synchronized with a switching timing of the first bit and the second bit of the Manchester-encoded digital signal. - View Dependent Claims (5, 6)
- 10”
-
7. A signal processing apparatus executing a decoding process for a digital signal Manchester-encoded by assigning two bits of “
- 10”
to any one of binary digital signals “
0 and “
1”
, and assigning two bits of “
01”
to the other binary digital signal, comprising;a decoding unit executing the decoding process with a processing unit corresponding to a term of two bits of the Manchester-encoded digital signal so as to detect only any one of a first bit and a second bit of the Manchester-encoded digital signal; a clock generating circuit generating a clock synchronized with a phase of the Manchester-encoded digital signal from the corresponding Manchester-encoded digital signal; and a binarizing circuit binarizing the Manchester-encoded digital signal to output the binarized Manchester-encoded digital signal to the decoding unit and the clock generating circuit, wherein the decoding unit extracts only the second bit of the Manchester-encoded digital signal output from the binarizing circuit at the falling edge or the rising edge of the clock output from the clock generating circuit. - View Dependent Claims (8)
- 10”
-
9. A signal transmitting system, comprising:
-
a transmitting unit including a Manchester-encoding unit generating a digital signal Manchester-encoded by assigning two hits of “
10”
to any one of binary digital signals “
0 and “
1”
of transmission data to be transmitted, and assigning two bits of “
01”
to the other binary digital signal; anda receiving unit including a decoding unit executing a decoding process for the Manchester-encoded digital signal with a processing unit corresponding to a term of two bits of the Manchester-encoded digital signal so as to detect only any one of a first bit and a second bit of the Manchester-encoded digital, wherein the decoding unit executes the decoding process for the Manchester-encoded digital signal by using only a circuit element operating as substantially phase-synchronized with a switching timing of the first bit and the second bit of the Manchester-encoded digital signal. - View Dependent Claims (10, 11, 12, 13, 14)
-
-
15. A signal processing method for a digital signal Manchester-encoded by assigning two bits of “
- 10”
to any one of binary digital signals “
0 and “
1”
, and assigning two bits of “
01”
to the other binary digital signal, comprising;a decoding step of executing a decoding process with a processing unit corresponding to a term of two bits of the Manchester-encoded digital signal so as to detect only any one of a first bit and a second bit of the Manchester-encoded digital signal; and a clock generating step of generating a clock phase-synchronized with the Manchester-encoded digital signal, wherein the decoding step extracts only the second bit of the Manchester-encoded digital signal at a falling edge or a rising edge of the clock generated by the clock generating step. - View Dependent Claims (16, 17)
- 10”
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeOlympus Corporation
-
Original AssigneeOlympus Corporation, Olympus Medical Systems Corporation (Olympus Corporation)
-
InventorsKato, Shuichi, Kawata, Susumu, Honda, Makoto
-
Primary Examiner(s)Singh, Hirdepal
-
Application NumberUS12/257,602Publication NumberTime in Patent Office1,656 DaysField of Search375/135, 375/136, 375/242, 375/316, 375/324, 375/342, 375/354, 375/359, 375/361US Class Current375/361CPC Class CodesH04B 13/005 Transmission systems in whi...H04L 25/4904 using self-synchronising co...
