Emulation of abstracted DIMMs using abstracted DRAMs

• US 8,438,328 B2
• Filed: 02/14/2009
• Issued: 05/07/2013
• Est. Priority Date: 02/21/2008
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Wang, David T., Smith, Michael J. S.
• Primary Examiner(s): Bragdon, Reginald
• Assistant Examiner(s): Bansal, Gurtej
• Application Number:
  US12/378,328
• Publication Number:
  US 20090216939A1
• Time in Patent Office: 1,543 Days
• Field of Search: 711/5, 711/105, 711/167, 365/189.2
• US Class Current: 711/105
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

Claims

1. An abstracted memory apparatus for emulation of memory comprising:

at least one memory system interface; and

at least one abstracted memory module, wherein each of the at least one abstracted memory modules comprises a first abstracted DRAM and a second abstracted DRAM;

wherein the first abstracted DRAM has a first address space disposed electrically behind a first intelligent buffer, and the second abstracted DRAM has a second address space disposed electrically behind a second intelligent buffer;

wherein the first intelligent buffer is operable to present to the memory system interface the first abstracted DRAM with a first emulated address space that is different from the first address space;

wherein the first intelligent buffer is operable to change dynamically one or more characteristics of the first emulated address space;

wherein the second intelligent buffer is operable to present to the memory system interface the second abstracted DRAM with a second emulated address space that is different from the second address space; and

wherein the first and second intelligent buffers emulate the respective abstracted DRAM so that protocol requirements and limitations required by the memory system interface based on the presented emulated address spaces are satisfied by the intelligent buffers.

2. The abstracted memory apparatus of claim 1 wherein the first intelligent buffer is operable to change dynamically one or more characteristics of the first emulated address space further comprises the first intelligent buffer is operable to present to the memory system interface the first emulated address space with a first set of characteristics during a first time period and with a second set of characteristics during a second time period;

and

wherein at least one characteristic presented in the second set of characteristics is different from the characteristic presented in the first set of characteristics.

3. The abstracted memory apparatus of claim 1, wherein the second intelligent buffer is operable to change dynamically one or more characteristics of the second emulated address space.

4. The abstracted memory apparatus of claim 3, wherein the one or more characteristics of the first emulated address space is different from the one or more characteristics of the second emulated address space.

5. The abstracted memory apparatus of claim 1, wherein the one or more characteristics of the first emulated address space include at least one of an address space, a plurality of address spaces, a protocol, a signaling scheme, a memory type, a power management rule, a power management mode, a power down operation, a timing characteristic, an address decoding option, an abstracted CS signal, an additional signal assertion, or a plane characteristic.

6. The abstracted memory apparatus of claim 5, wherein the memory type includes at least one of a DDR2 memory, a DDR3 memory, a GDDR5 memory, a LPDDR2 memory, a GDDR3 memory, a NOR flash memory, or a NAND flash memory.

7. The abstracted memory apparatus of claim 5, wherein the memory type presented to the memory system interface is different from a memory type of a first physical DRAM connected to the first intelligent buffer, and wherein the first intelligent buffer is operable to emulate the first abstract DRAM based on the first physical DRAM.

8. The abstracted memory apparatus of claim 5, wherein the timing characteristic includes at least one of a tRP timing, a tRCD timing, a TWL timing, a tRFC timing, a tCKE timing, a tXP timing, a tXARD timing, a TXRDS timing, a tAL timing, a tFAW timing, a tRAS timing, a tRC timing, a tRRD timing, a tRTP timing, a tWR timing, or a tWTR timing.

9. The abstracted memory apparatus of claim 5, wherein the power management mode includes at least one of a CKE-after-ACT power management mode, a CKE-after-precharge power management mode, a precharge powerdown mode, or a self refresh mode.

10. The abstracted memory apparatus of claim 5, wherein the power management mode includes at least one of asserting a CKE input or deasserting a CKE input.

11. The abstracted memory apparatus of claim 5, wherein the power down operation includes at least one of entry into a precharge power down operation, exit from precharge power down mode, a fast exit active power down mode, or a slow exit active power down mode.

12. The abstracted memory apparatus of claim 5, wherein the additional signal includes at least one of a signal to switch to aggressive power management mode or a signal to switch to a longer timing parameter signal.

13. The abstracted memory apparatus of claim 5 wherein the protocol includes at least one of an industry-standard protocol, a protocol extension to an industry-standard protocol, a combination of bits, or a combination of fields.

14. The abstracted memory apparatus of claim 5, wherein the plane characteristic includes at least one of a vertically stacked plane characteristic, a number of planes, a power plane characteristic, a performance plane characteristic, a reliability plane characteristic, a RAS plane characteristic, a timing parameter plane characteristic, or a hierarchical arrangement characteristic.

15. The abstracted memory apparatus of claim 1, wherein the first intelligent buffer is operable to present to the memory system interface a first abstracted DIMM, and wherein the first abstracted DIMM includes the first abstracted DRAM.

16. The abstracted memory apparatus of claim 15, wherein the first intelligent buffer is operable to present to the memory system interface a first abstracted DIMM further comprises the first intelligent buffer is operable to emulate the first abstracted DIMM based on at least one physical DIMM disposed on a single PCB and to present the emulated first abstracted DIMM to the memory system interface.

17. The abstracted memory apparatus of claim 16 wherein the at least one physical DIMM is directly connected to the first intelligent buffer.

18. The abstracted memory apparatus of claim 15, wherein the second intelligent buffer is operable to present to the memory system interface a second abstracted DIMM, and wherein the second abstracted DIMM includes the second abstracted DRAM.

19. The abstracted memory apparatus of claim 18 wherein the first abstracted DIMM is larger in memory capacity than the second abstracted DIMM.

20. The abstracted memory apparatus of claim 18 wherein the first intelligent buffer is operable to merge data from the first abstracted DIMM with data from the second abstracted DIMM into a continuous stream and to present the merged data to the memory system interface.

21. The abstracted memory apparatus of claim 18 wherein a CS signal presented to the first abstracted DIMM is the same CS signal as is presented to the second abstracted DIMM.

22. An abstracted memory apparatus for emulation of memory comprising:

at least one memory system interface;

at least one abstracted memory module, wherein each of the at least one abstracted memory modules comprises a first abstracted DRAM and a second abstracted DRAM;

wherein the first abstracted DRAM has a first address space disposed electrically behind a first intelligent buffer, and the second abstracted DRAM has a second address space disposed electrically behind a second intelligent buffer;

wherein the first intelligent buffer is operable to present to the memory system interface the first abstracted DRAM with a first emulated address space that is different from the first address space;

wherein the first intelligent buffer is operable to change dynamically one or more characteristics of the first emulated address space;

wherein the second intelligent buffer is operable to present to the memory system interface the second abstracted DRAM with a second emulated address space that is different from the second address space; and

wherein the first and second intelligent buffers emulate the respective abstracted DRAM so that protocol requirements and limitations required by the memory system interface based on the presented emulated address spaces are satisfied by the intelligent buffers; and

at least one motherboard.

23. The abstracted memory apparatus of claim 22, further comprising at least one of a memory controller, a processor section, a processor, a blade, or a platform chassis.

24. The abstracted memory apparatus of claim 22, wherein the first intelligent buffer is operable to present to the memory system interface a first abstracted DIMM further comprises the first intelligent buffer is operable to emulate the first abstracted DIMM based on at least one physical DIMM disposed on a single PCB and to present the emulated first abstracted DIMM to the memory system interface.

25. The abstracted memory apparatus of claim 22, wherein the first intelligent buffer is operable to change dynamically one or more characteristics of the first emulated address space further comprises the first intelligent buffer is operable to present to the memory system interface the first emulated address space with a first set of characteristics during a first time period and with a second set of characteristics during a second time period;

and

wherein at least one characteristic presented in the second set of characteristics is different from a characteristic presented in the first set of characteristics.

26. The abstracted memory apparatus of claim 22, wherein the second intelligent buffer is operable to change dynamically one or more characteristics of the second emulated address space.

27. The abstracted memory apparatus of claim 26, wherein the one or more characteristics of the first emulated address space is different from the one or more characteristics of the second emulated address space.

28. The abstracted memory apparatus of claim 22, wherein the first intelligent buffer is operable to present to the memory system interface a first abstracted DIMM, and wherein the first abstracted DIMM includes the first abstracted DRAM.

29. The abstracted memory apparatus of claim 28, wherein the second intelligent buffer is operable to present to the memory system interface a second abstracted DIMM, and wherein the second abstracted DIMM includes the second abstracted DRAM.

30. The abstracted memory apparatus of claim 29, wherein the first intelligent buffer is operable to merge data from the first abstracted DIMM with data from the second abstracted DIMM into a continuous stream and to present the merged data to the memory system interface.