Enhanced diagnosis with limited failure cycles

• US 8,438,438 B2
• Filed: 11/17/2010
• Issued: 05/07/2013
• Est. Priority Date: 02/17/2006
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Huang, Yu, Cheng, Wu-Tung, Tamarapalli, Nagesh, Klingenberg, Randy, Rajski, Janusz
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US12/948,460
• Publication Number:
  US 20110126064A1
• Time in Patent Office: 902 Days
• Field of Search: 714/726, 714/729, 714/742
• US Class Current: 714/726
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318569 Error indication, logging circuits

Abstract

Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which can be used to measure chain or logic diagnosability of the pattern set. Per-pin based diagnosis techniques can also be used to analyze limited failure data.

Claims

1. A method for an electronic circuit design, the design comprising one or more scan chains with a plurality of scan cells, the method comprising:

receiving one or more coverage scores for one or more of the scan cells, the coverage scores being associated with one or more scan patterns;

determining, according to the one or more coverage scores, a diagnosis coverage figure for at least one scan chain of the one or more scan chains in relation to the one or more scan patterns, wherein the diagnosis coverage figure indicates a likelihood of detecting scan chain defects in the at least one scan chain using the one or more scan patterns; and

storing the diagnosis coverage figure.

2. The method of claim 1, further comprising ordering at least some of the scan patterns according to their respective diagnosis coverage figures.

3. The method of claim 2, further comprising:

loading at least some of the scan patterns into the one or more scan chains; and

testing the one or more scan chains using the loaded patterns.

4. The method of claim 3, further comprising providing results of the testing to a per-pin based tester.

5. The method of claim 3, further comprising providing results of the testing to a per-cycle based tester.

6. The method of claim 1, further comprising identifying one or more failing scan chains and thereafter determining one or more diagnostic coverage figures for the failing scan chains.

7. The method of claim 1, wherein determining one or more diagnosis coverage figures comprises averaging two or more of the coverage scores.

8. The method of claim 1, wherein the at least one scan chain comprises a first scan chain with a first plurality of scan cells and a second scan chain with a second plurality of scan cells, wherein the coverage scores are for at least one scan cell of the first plurality of scan cells and at least one scan cell of the second plurality of scan cells, and wherein the diagnosis coverage score is determined for both the first scan chain and the second scan chain.

9. A method for an electronic circuit design, the design comprising one or more system logic sections, the method comprising:

determining one or more diagnosis coverage figures for one or more test patterns in a set of test patterns, wherein the diagnosis coverage figure is based at least in part on a number of fault pairs in the one or more system logic sections distinguished by the one or more patterns;

ordering at least some of the patterns based at least in part on the one or more diagnosis coverage figures; and

storing the ordered patterns.

10. The method of claim 9, wherein the number of fault pairs distinguished by the one or more patterns is a number of suspect fault pairs in the one or more system logic sections distinguished by the one or more patterns.

11. One or more computer-readable storage media having encoded thereon instructions which, when executed by a computer, cause the computer to perform a method for an electronic circuit design, the design comprising one or more scan chains with a plurality of scan cells, the method comprising:

receiving one or more coverage scores for one or more of the scan cells, the coverage scores being associated with one or more scan patterns; and

determining, according to the one or more coverage scores, a diagnosis coverage figure for at least one scan chain of the one or more scan chains in relation to the one or more scan patterns, wherein the diagnosis coverage figure indicates a likelihood of detecting scan chain defects in the at least one scan chain using the one or more scan patterns.

12. The one or more computer-readable storage media of claim 11, the method further comprising ordering at least some of the scan patterns according to their respective diagnosis coverage figures.

13. The one or more computer-readable storage media of claim 12, the method further comprising:

loading at least some of the scan patterns into the one or more scan chains; and

testing the one or more scan chains using the loaded patterns.

14. The one or more computer-readable storage media of claim 13, the method further comprising providing results of the testing to a per-pin based tester.

15. The one or more computer-readable storage media of claim 13, the method further comprising providing results of the testing to a per-cycle based tester.

16. The one or more computer-readable storage media of claim 11, the method further comprising identifying one or more failing scan chains and thereafter determining one or more diagnostic coverage figures for the failing scan chains.

17. The one or more computer-readable storage media of claim 11, wherein determining one or more diagnosis coverage figures comprises averaging two or more of the coverage scores.

18. The one or more computer-readable storage media of claim 11, wherein the at least one scan chain comprises a first scan chain with a first plurality of scan cells and a second scan chain with a second plurality of scan cells, wherein the coverage scores are for at least one scan cell of the first plurality of scan cells and at least one scan cell of the second plurality of scan cells, and wherein the diagnosis coverage score is determined for both the first scan chain and the second scan chain.

19. One or more computer-readable storage media having encoded thereon instructions which, when executed by a computer, cause the computer to perform a method for an electronic circuit design, the design comprising one or more system logic sections, the method comprising:

determining one or more diagnosis coverage figures for one or more test patterns in a set of test patterns, wherein the diagnosis coverage figure is based at least in part on a number of fault pairs in the one or more system logic sections distinguished by the one or more patterns; and

ordering at least some of the patterns based at least in part on the one or more diagnosis coverage figures.

20. The one or more computer-readable storage media of claim 19, wherein the number of fault pairs distinguished by the one or more patterns is a number of suspect fault pairs in the one or more system logic sections distinguished by the one or more patterns.