Low latency read operation for managed non-volatile memory

• US 8,438,453 B2
• Filed: 08/07/2009
• Issued: 05/07/2013
• Est. Priority Date: 05/06/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Post, Daniel Jeffrey, Wakrat, Nir Jacob, Khmelnitsky, Vadim
• Primary Examiner(s): Merant, Guerrier
• Application Number:
  US12/538,053
• Publication Number:
  US 20100287446A1
• Time in Patent Office: 1,369 Days
• Field of Search: None
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

In a memory system, a host controller is coupled to a non-volatile memory (NVM) package (e.g., NAND device). The host controller sends a read command to the NVM package requesting a low latency read operation. Responsive to the read command, a controller in the NVM package retrieves the data and sends the data to an ECC engine for correcting. Following the read command, the host controller sends a read status request command to the controller in the NVM package. Responsive to the read status request, the controller sends a status report to the host controller indicating that some or all of the data is available for transfer to the host controller. Responsive to the report, the host controller transfers the data. An underrun status can be determined to indicate that uncorrected data had been transferred to the host controller.

Claims

1. A non-volatile memory (NVM) device, comprising:

an interface configured to receive a read command and a read status request from a host controller;

a number of concurrently addressable memory units each containing a number of blocks, wherein each concurrently addressable unit is configured to be simultaneously readable with respect to the other concurrently addressable memory units, and wherein the read command specifies one or more blocks of one or more of the concurrently addressable memory units from which to read data;

a controller coupled to the interface and the number of concurrently addressable memory units, the controller configured to;

read data from the one or more blocks of the one or more concurrently addressable memory units specified by the read command;

error correct a portion of the data;

make the error corrected portion of the data available for transferring to the host controller prior to making another portion of the data available for transfer; and

respond to the read status request with information indicating that the error corrected portion of the data is available for transfer.

2. The device of claim 1, where the information includes one or more bits indicating an error correcting code delay.

3. The device of claim 1, where the information includes one or more bits indicating that data was properly read from a memory array of the NVM device.

4. The device of claim 1, where the information includes one or more bits indicating that data is ready to be transferred from the NVM device to the host controller.

21. The method of claim 1, where the information includes an underrun status.

22. The method of claim 1, where the information includes an indication of whether the data was correctable.

5. A host controller configured for coupling with a non-volatile memory (NVM) device, comprising:

an interface configured to couple to the NVM device; and

a controller coupled to the interface and configured to;

send a read command and a read status request to the NVM device;

receive, in response to the read status request, information indicating that an error corrected portion of the data is available for transfer to the controller prior to another portion of the data being available for transfer; and

transfer the error corrected portion of data from the NVM to the controller, prior to transferring another portion of the data.

6. A method performed by a non-volatile memory (NVM) device, the method comprising:

receiving a read command and a read status request from a host controller coupled to the NVM device;

reading data from a number of concurrently addressable memory units in the NVM device that are identified by the read command, wherein each concurrently addressable unit is configured to be simultaneously readable with respect to the other concurrently addressable memory units;

error correcting a portion of the data to be read; and

making the error corrected portion of data available for transferring to the host controller prior to making another portion of the data available for transfer; and

responding to the read status request with information indicating that the error corrected portion of data is available for transfer.

7. The method of claim 6, where the information includes one or more bits indicating an error correcting code delay.

8. The method of claim 6, where the information includes one or more bits indicating that data was properly read from a memory array of the NVM device.

9. The method of claim 6, where the information includes one or more bits indicating that data is ready to be transferred from the NVM device to the host controller.

10. A method performed by a host controller configured for coupling with a non-volatile memory (NVM) device, the method comprising:

sending a read command and a read status request to the NVM device;

receiving, in response to the read status request, information indicating that an error corrected portion of data to be read is available for transfer to the host controller prior to another portion of the data being available for transfer; and

transferring the error corrected portion of the data from the NVM device to the host controller prior to transferring another portion of the data.

11. The method of claim 10, where the information received in response to the read status request also includes one or more of an underrun status or an indication of whether the data was correctable and the host controller sends another read command to the NVM device in response to the information.

12. The method of claim 10, where the information includes one or more bits indicating an error correcting code delay.

13. The method of claim 10, where the information received in response to the read status request includes one or more bits indicating that data was properly read from the NVM device.

14. The method of claim 10, where the information received in response to the read status request includes one or more bits indicating that data is ready to be transferred from the NVM device to the host controller.

15. The method of claim 10, where the information received in response to the read status request is received before or after a portion of the data is transferred to the host controller.

16. The method of claim 10, where the information received in response to the read status request indicates a number of error correcting code segments available for transfer to the host controller.

17. A memory system, comprising:

a host controller;

a non-volatile memory (NVM) device;

an interface coupling the host controller and the NVM device, the host controller configured to send a read command and a read status request to the NVM device over the interface;

a number of concurrently addressable memory units included in the NVM device, the memory units containing a number of blocks, wherein each concurrently addressable unit is configured to be simultaneously readable with respect to the other concurrently addressable memory units and wherein the read command specifies one or more blocks of one or more of the concurrently addressable memory units from which to read data;

a controller of the NVM device coupled to the number of concurrently addressable memory units, the controller configured to;

read data from the number of blocks of the number of concurrently addressable memory units specified by the read command;

error correct a portion of the data; and

make the error corrected portion of the data available for transferring from the NVM device to the host controller over the interface prior to another portion to making another portion of the data available for transfer; and

respond to the read status request with information indicating that the error corrected portion of the data is available for transfer.

18. The system of claim 17, where the information includes one or more bits indicating that data is ready to be transferred from the NVM device to the host controller.

19. The system of claim 17, where the information can be sent to the NVM device before or after data is transferred to the host controller.

20. The system of claim 17, where the information indicates a number of error correcting code segments available for transfer to the host controller.