Error correction in a solid state disk

• US 8,438,455 B2
• Filed: 12/31/2008
• Issued: 05/07/2013
• Est. Priority Date: 12/31/2008
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Vogan, Andrew Wayne, Coulson, Richard
• Primary Examiner(s): DUNCAN, MARC M
• Application Number:
  US12/319,208
• Publication Number:
  US 20100169743A1
• Time in Patent Office: 1,588 Days
• Field of Search: 714/763, 714/764, 714/773, 714/800, 714/803
• US Class Current: 714/764
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence
• CPC Class Codes: G11B 2220/61 wherein solid state memory is used for storing A/V content

Abstract

In some embodiments, a solid state disk includes a non-volatile memory and a controller. The controller performs ECC on data stored on the non-volatile memory, and performs a parity operation on the data if the ECC cannot correct the data. Other embodiments are described and claimed.

Claims

1. A solid state disk comprising:

non-volatile memory made up of a plurality of memory die, wherein each memory die includes a plurality of sectors, and wherein a plurality of pages are formed from a subset of the plurality of sectors for each of the plurality of memory die; and

a controller to

write data to the non-volatile memory, wherein the data is written to a page in chronological order through the plurality of memory die and sector by sector to the memory die;

generate error correction code (ECC) on the data written to the non-volatile memory;

perform a parity operation on the data contained in corresponding sectors of the plurality of memory die; and

write the parity data to at least one of the plurality of memory die in a corresponding sector.

2. The solid state disk of claim 1, wherein the controller is further to generate replacement data from parity data for data that contains errors and cannot be corrected using the ECC.

3. The solid state disk of claim 1, wherein the controller performs the parity operation as an XOR operation.

4. The solid state disk of claim 1, wherein the plurality of memory die are capable of concurrent work.

5. The solid state disk of claim 1, wherein one or more of the plurality of memory die are reserved for parity information.

6. The solid state disk of claim 1, wherein the non-volatile memory is made up of a plurality of NAND die.

7. The solid state disk of claim 1, wherein one or more of the plurality of memory die are NAND die.

8. A system comprising:

a host; and

a solid state disk including;

non-volatile memory made up of a plurality of memory die, wherein each memory die includes a plurality of sectors, and wherein a plurality of pages are formed from a subset of the plurality of sectors for each of the plurality of memory die; and

a controller to

write data to the non-volatile memory, wherein the data is written to a page in chronological order through the plurality of memory die and sector by sector to the memory die,

generate error correction code (ECC) on the data written to the non-volatile memory,

perform a parity operation on the data contained in corresponding sectors of the plurality of memory die; and

write the parity data to at least one of the plurality of memory die in a corresponding sector.

9. The system of claim 8, wherein the controller is further to generate replacement data from parity data for data that contains errors and cannot be corrected using the ECC.

10. The system of claim 8, wherein the controller performs the parity operation as an XOR operation.

11. The system of claim 8, wherein the plurality of memory die are capable of being written to concurrently.

12. The system of claim 8, wherein one or more of the plurality of memory die are reserved for parity information.

13. The system of claim 8, wherein the non-volatile memory is made up of a plurality of NAND die.

14. The system of claim 8, wherein one or more of the plurality of memory die are NAND die.

15. A method comprising:

writing data to a non-volatile memory, wherein the non-volatile memory includes a plurality of memory die, wherein each memory die includes a plurality of sectors, wherein a plurality of pages are formed from a subset of the plurality of sectors for each of the plurality of memory die, and wherein the data is written to a page in chronological order through the plurality of memory die and sector by sector to the memory die;

generating error correction code (ECC) on the data written to the non-volatile memory;

performing a parity operation on the data contained in corresponding sectors of the plurality of memory die; and

writing the parity data to at least one of the plurality of memory die in a corresponding sector.

16. The method of claim 15, further comprising generating replacement data from parity data for data that contains errors and cannot be corrected using the ECC.

17. The method of claim 15, wherein the performing a parity operation including performing an XOR operation on the data in corresponding sectors.

18. The method of claim 15, wherein the plurality of memory die are capable of being written to concurrently.

19. The method of claim 15, wherein one or more of the plurality of memory die are reserved for parity information.

20. The method of claim 15, wherein the non-volatile memory includes a plurality of NAND die.

21. The method of claim 15, wherein one or more of the plurality of memory die are NAND die.