Hierarchical editing of printed circuit board pin assignment

• US 8,438,524 B1
• Filed: 12/30/2009
• Issued: 05/07/2013
• Est. Priority Date: 12/30/2009
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Kohli, Vikas, Durrill, Steven R.
• Primary Examiner(s): Do, Thuan
• Assistant Examiner(s): Alam, Mohammed
• Application Number:
  US12/650,352
• Time in Patent Office: 1,224 Days
• Field of Search: 716/120, 716/126
• US Class Current: 716/120
• CPC Class Codes: G06F 2113/18 Chip packaging
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

An interface object library tool for manipulating interface objects for a printed circuit board (PCB) tool is disclosed. The interface object library tool includes a hierarchical interface display module, an input module, and a store. The hierarchical interface display module is configured to display an interrelation between a plurality of interface objects and a plurality of groups each including a plurality of signal, power and ground lines. The plurality of interface objects are configured to be associated with a plurality of block objects to define a plurality of component objects. The input module is configured to: accept association of the plurality of groups and the plurality of signal, power and ground lines without defining pin or pad assignments; and accept association between the plurality of interface objects and a plurality of groups. The store is configured to retain the plurality of interface objects; the plurality of groups; the plurality of signal, power and ground lines; and associations between these three.

Claims

1. A system for printed circuit board (PCB) pin assignment, the system comprising:

a hierarchical interface display module configured to display an interrelation between a plurality of interface objects and a plurality of groups each including a plurality of signal, power and ground lines, each of the interface objects including a group or sub-groups of signals, wherein the plurality of interface objects are configured to be associated with a plurality of block objects to define a plurality of component objects which are parts that are added to a PCB;

an input module configured to;

accept association of the plurality of groups and the plurality of signal, power and ground lines without defining pin or pad assignments, and

accept association between the plurality of interface objects and a plurality of groups; and

a store configured to retain;

the plurality of interface objects;

the plurality of groups;

the plurality of signal, power and ground lines; and

associations between these three.

2. The system as recited in claim 1, wherein the plurality of component objects include a custom component object that has a physical object with configurable pin or pad assignments.

3. The system as recited in claim 1, wherein the interrelation is according to a hierarchy having a plurality of levels of abstraction.

4. The system as recited in claim 1, wherein the store is further configured to retain the component objects.

5. The system as recited in claim 1, wherein the PCB tool includes a display module that interfaces to the hierarchical interface display module to accentuate groups of pins or pads according to a hierarchy of an interface object.

6. The system as recited in claim 1, wherein:

an interface object has several different versions, and

the input module is configured to receive selection of the several variations.

7. The system as recited in claim 1, wherein a group of the plurality of groups comprises a plurality of sub-groups, which each contain a plurality of signal, power and ground lines.

8. The system as recited in claim 1, wherein the input module is configured to receive one or more rules associated with a group, signal line, power line, ground line, package, and/or connector that affects pin assignment within a group or to a physical object.

9. A computer-implemented method for manipulating interface objects for a PCB tool, the method comprising:

accepting, using an input module of a computer system, association of the plurality of groups and the plurality of signal, power and ground lines without defining pin or pad assignments;

accepting, using an input module of a computer system, association between the plurality of interface objects and a plurality of groups, each of the interface objects including a group or sub-groups of signals;

storing;

the plurality of interface objects;

the plurality of groups;

the plurality of signal, power and ground lines; and

,

associations between these three; and

displaying an interrelation between a plurality of interface objects and a plurality of groups each including a plurality of signal, power and ground lines, wherein the plurality of interface objects are configured to be associated with a plurality of block objects to define a plurality of component objects.

10. The computer-implemented method for manipulating interface objects for the PCB tool as recited in claim 9, wherein the interrelation is according to a hierarchy with every level above a current level includes more pins.

11. The computer-implemented method for manipulating interface objects for the PCB tool as recited in claim 9, wherein:

the plurality of component objects include a custom package that has configurable pin or pad assignments; and

the method further comprises displaying the interrelation between pins or pads and the plurality of groups.

12. The computer-implemented method for manipulating interface objects for the PCB tool as recited in claim 9, further comprising storing the plurality of component objects.

13. The computer-implemented method for manipulating interface objects for the PCB tool as recited in claim 9, further comprising:

interfacing a display module to the hierarchical interface display module; and

accentuating groups of pins or pads according to a hierarchy of an interface object.

14. The computer-implemented method for manipulating interface objects for the PCB tool as recited in claim 9, wherein:

an interface object has several different versions, and

the method further comprises receiving selection of the several variations.

15. The computer-implemented method for manipulating interface objects for the PCB tool as recited in claim 9, wherein a group of the plurality of groups comprises a plurality of sub-groups, which each contain a plurality of signal, power and ground lines.

16. The computer-implemented method for manipulating interface objects for the PCB tool as recited in claim 9, further comprising receiving one or more rules associated with a group, signal line, power line, ground line, package, and/or connector that affects pin assignment within a group or to a package or connector.

17. A non-transitory machine-readable storage medium comprising executable instructions for manipulating interface objects for a PCB tool, comprising code for:

accepting association of the plurality of groups and the plurality of signal, power and ground lines without necessarily defining pin or pad assignments;

accepting association between the plurality of interface objects and a plurality of groups, each of the interface objects including a group or sub-groups of signals;

storing;

the plurality of interface objects;

the plurality of groups;

the plurality of signal, power and ground lines; and

,

associations between these three; and

displaying an interrelation between a plurality of interface objects and a plurality of groups each including a plurality of signal, power and ground lines, wherein the plurality of interface objects are configured to be associated with a plurality of component objects, which correspond to a plurality of physical objects.

18. The non-transitory machine-readable storage medium comprising executable instructions for manipulating interface objects for the PCB tool as recited in claim 17, wherein:

the plurality of physical objects include a custom package that has configurable pin or pad assignments; and

the machine-readable storage medium further comprises code for displaying the interrelation between pins or pads and the plurality of groups.

19. The non-transitory machine-readable storage medium comprising executable instructions for manipulating interface objects for the PCB tool as recited in claim 17, wherein the interrelation is according to a hierarchy with every level above a current level includes more pins.

20. The non-transitory machine-readable storage medium comprising executable instructions for manipulating interface objects for the PCB tool as recited in claim 17, the machine-readable storage medium further comprises code for storing the plurality of component objects.

21. The non-transitory machine-readable storage medium comprising executable instructions for manipulating interface objects for the PCB tool as recited in claim 17, the machine-readable storage medium further comprises code for:

interfacing a display module to the hierarchical interface display module; and

accentuating groups of pins or pads according to a hierarchy of an interface object.

22. The non-transitory machine-readable storage medium comprising executable instructions for manipulating interface objects for the PCB tool as recited in claim 17, wherein:

an interface object has several different versions, and

the machine-readable storage medium further comprises code for receiving selection of the several variations.

23. The non-transitory machine-readable storage medium comprising executable instructions for manipulating interface objects for the PCB tool as recited in claim 17, wherein a group of the plurality of groups comprises a plurality of sub-groups, which each contain a plurality of signal, power and ground lines.

24. The non-transitory machine-readable storage medium comprising executable instructions for manipulating interface objects for the PCB tool as recited in claim 17, the machine-readable storage medium further comprises code for receiving one or more rules associated with a group, signal line, power line, ground line, package, and/or connector that affects pin assignment within a group or to a package or connector.