Network on chip with an I/O accelerator

• US 8,438,578 B2
• Filed: 06/09/2008
• Issued: 05/07/2013
• Est. Priority Date: 06/09/2008
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hoover, Russell D., Kriegel, Jon K., Mejdrich, Eric O.
• Primary Examiner(s): Sough, S.
• Assistant Examiner(s): DORAIS, CRAIG C
• Application Number:
  US12/135,364
• Publication Number:
  US 20090307714A1
• Time in Patent Office: 1,793 Days
• Field of Search: None
• US Class Current: 719/313
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00

Abstract

Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator that administers at least some data communications traffic to and from the at least one IP block.

Claims

1. A network on chip (‘

NOC’

) comprising;

IP blocks, routers, memory communications controllers, and network interface controllers;

each IP block adapted to a router through a memory communications controller and a network interface controller;

each memory communications controller for controlling communication between an IP block and memory;

each network interface controller for controlling inter-IP block communications through said routers;

each IP block adapted to the NOC by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox;

a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and

at least one of the IP blocks comprising an input/output (‘

I/O’

) accelerator configured to administer at least some data communications traffic to and from the at least one IP block,

wherein the I/O accelerator further comprises;

an aggregation of sequential and non-sequential logic configured to function in response to a single opcode executed on a thread of execution on a processor in the at least one IP block that comprises the I/O accelerator to receive a plurality of messages through the inbox in accordance with an application pipeline protocol, convert data from the messages from message format to I/O format, and perform multiple store operations of the converted data.

2. The NOC of claim 1 wherein the I/O accelerator further comprises:

an aggregation of sequential and non-sequential logic configured to function in response to a single opcode executed on a thread of execution on a processor in the at least one IP block that comprises the I/O accelerator to perform multiple load operations of data from said memory, formulate the loaded data into a plurality of messages according to an application pipeline protocol, and send the plurality of messages through the outbox according to the application pipeline protocol.

3. The NOC of claim 1 wherein the computer software application segmented into stages further comprises the stages load balanced with a number of instances of each stage in dependence upon the performance of the stages.

4. The NOC of claim 1 wherein each outbox comprises an array indexed by an outbox write pointer and an outbox read pointer, the outbox further comprising an outbox message controller enabled to set the outbox write pointer, set the outbox read pointer, and send to the network message data written into the array by a thread of execution associated with the outbox.

5. The NOC of claim 4 wherein the thread of execution is enabled to provide message control information, including destination identification and an indication that data in the array is ready to be sent.

6. The NOC of claim 1 wherein each inbox comprises an array indexed by an inbox write pointer and an inbox read pointer, the inbox further comprising an inbox message controller enabled to set the inbox write pointer, set the inbox read pointer, receive from the network message data written to the network from another outbox of another IP block, and provide to a thread of execution associated with the inbox the message data received from the network.

7. The NOC of claim 6 wherein the inbox message controller is enabled to notify the thread of execution associated with the inbox that message data has been received from the network.

8. The NOC of claim 1 wherein each IP block comprises a reusable unit of synchronous or asynchronous logic design used as a building block for data processing within the NOC.

9. The NOC of claim 1 wherein each network interface controller is enabled to:

convert communications instructions from command format to network packet format;

and implement virtual channels on the network, characterizing network packets by type.

10. A method of data processing with a network on chip (‘

NOC’

), the NOC comprising integrated processor (‘

IP’

) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, each IP block adapted to the NOC by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox, at least one of the IP blocks comprising an input/output (‘

I/O’

) accelerator, the method comprising;

controlling by each memory communications controller communications between an IP block and memory;

controlling by each network interface controller inter-IP block communications through said routers;

segmenting a computer software application into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID;

executing each stage on a thread of execution on an IP block; and

administering

by the I/O accelerator at least some data communications traffic to and from the at least one IP block,

wherein administering by the I/O accelerator at least some data communications traffic to and from the at least one IP block further comprises, in response to a single opcode executed on a thread of execution on a processor in the at least one IP block comprising the I/O accelerator;

receiving a plurality of messages through the inbox according to an application pipeline protocol;

converting data from the messages from message format to I/O format; and

performing multiple store operations of the converted data.

11. The method of claim 10 wherein administering by the I/O accelerator at least some data communications traffic to and from the at least one IP block further comprises, in response to a single opcode executed on a thread of execution on a processor in the at least one IP block comprising the I/O accelerator:

performing multiple load operations of data from said memory;

formulating loaded data into a plurality of messages according to an application pipeline protocol; and

sending the plurality of messages through the outbox according to the application pipeline protocol.

12. The method of claim 10 wherein segmenting a computer software application into stages further comprises configuring each stage with a stage ID for each instance of a next stage.

13. The method of claim 10 wherein each outbox comprises an array indexed by an outbox write pointer and an outbox read pointer, the outbox further comprises an outbox message controller, and the method further comprises:

setting by the outbox message controller the outbox write pointer;

setting by the outbox message controller the outbox read pointer; and

sending, by the outbox message controller to the network, message data written into the array by a thread of execution associated with the outbox.

14. The method of claim 13 further comprising providing, to the outbox message controller by the thread of execution, message control information, including destination identification and an indication that data in the array is ready to be sent.

15. The method of claim 10 wherein each inbox comprises an array indexed by an inbox write pointer and an inbox read pointer, the inbox further comprising an inbox message controller, the method further comprising:

setting by the inbox message controller the inbox write pointer;

setting by the inbox message controller the inbox read pointer;

receiving, by the inbox message controller from the network, message data written to the network from another outbox of another IP block; and

providing, by the inbox message controller to a thread of execution associated with the inbox, the message data received from the network.

16. The method of claim 15 further comprising notifying, by the inbox message controller the thread of execution associated with the inbox, that message data has been received from the network.

17. The method of claim 10 wherein each IP block comprises a reusable unit of synchronous or asynchronous logic design used as a building block for data processing within the NOC.

18. The method of claim 10 wherein controlling inter-IP block communications further comprises:

converting by each network interface controller communications instructions from command format to network packet format; and

implementing by each network interface controller virtual channels on the network, characterizing network packets by type.