Microelectronic package and method for a compression-based mid-level interconnect

• US 8,440,506 B2
• Filed: 07/11/2012
• Issued: 05/14/2013
• Est. Priority Date: 12/23/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Roberts, Brent M., Roy, Mihir K., Sriniyasan, Sriram, Narasimhan, Sridhar
• Primary Examiner(s): Parekh, Nitin
• Application Number:
  US13/546,549
• Publication Number:
  US 20120279059A1
• Time in Patent Office: 307 Days
• Field of Search: 438/117, 438/107, 438/109, 257/E21.506
• US Class Current: 438/117
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: Y10T 29/49133 with component orienting

Abstract

A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

Claims

1. A method of comprising:

providing a first substrate comprising first level interconnects having a first pitch at a first surface thereof and a set of first contact pads having a second pitch at a second surface thereof;

providing a second substrate comprising a first surface comprising a set of second contact pads having the second pitch;

aligning a mid-level interconnect between the first and second substrates;

compressing the first and second substrates to actuate opposing arms of the mid-level interconnect to engage each respective surface of the corresponding first and second contact pads of the first and second substrates to form a substrate assembly; and

attaching a die to the substrate assembly.

2. The method of claim 1 further comprising:

vertically aligning the set of contact pads of the first surface with the set of contact pads at the second surface of the first substrate, and

using opposing compression-based pins of the mid-level interconnects to activate a surface of the corresponding first and second contact pads of the first and second substrates to provide micro-connections therebetween.

3. The method of claim 1 which compressing further comprises:

aligning a first portion of the opposing arms of the mid-level interconnect with the corresponding contact pads of the second substrate; and

actuating the first portion of the opposing arms with a load to activate a surface of the corresponding contact pads of the second substrate to provide a reusable surface mount attachment between the second substrate and the mid-level interconnect.

4. The method of claim 3 further comprising:

aligning a second portion of the opposing arms of the mid-level interconnect with the corresponding contact pads of the first substrate; and

actuating a second portion of the opposing arms with a load to activate a surface of the corresponding contact pads of the second substrate to provide a reusable surface mount attachment between the first substrate and the mid-level interconnect.

5. The method of claim 1 wherein:

releasing a load on the mid-level interconnect to disengage the first substrate from the mid-level interconnect;

replacing the first substrate with a patch including an attached chipset; and

actuating opposing arms of the mid-level interconnect to engage a respective surface of the contact pads of the patch to form an upgraded substrate assembly.

6. The method of claim 1 wherein:

a surface area of the second surface of the first substrate is smaller than a surface area of the first surface of the second substrate.

7. The method of claim 1 wherein the mid-level interconnect comprises:

a housing comprising opposing arms according to the second pitch; and

further comprising;

actuating the opposing arms to provide micro-connections with the corresponding first and second contact pads of the first and second substrates when actuated with a load.

8. The method of claim 7, wherein the opposing arms comprise flange-shaped pins.

9. The method of claim 1 wherein the housing comprises:

one or more through-hole posts to provide a load to compress and actuate a double compression mid-level interconnect.

10. The method of claim 1, further comprising:

coupling first level interconnects having the first pitch at a first surface of the microelectronic die to the first level interconnects of the first surface of the first substrate; and

coupling first level interconnects having the third pitch at a first surface of the motherboard to the second level interconnects at the second surface of the second substrate.

11. A method of comprising:

providing a first substrate comprising first level interconnects having a first pitch at a first surface thereof and a set of first contact pads having a second pitch at a second surface thereof;

providing a second substrate comprising a first surface comprising a set of second contact pads having the second pitch;

aligning a mid-level interconnect between the first and second substrates;

compressing the first and second substrates to actuate opposing arms of the mid-level interconnect to engage each respective surface of the corresponding first and second contact pads of the first and second substrates to form a substrate assembly; and

coupling a die to the first substrate using the first level interconnects.

12. The method of claim 11 further comprising:

vertically aligning the set of contact pads of the first surface with the set of contact pads at the second surface of the first substrate, and

using opposing compression-based pins of the mid-level interconnects to activate a surface of the corresponding first and second contact pads of the first and second substrates to provide micro-connections therebetween.

13. The method of claim 11 which compressing further comprises:

aligning a first portion of the opposing arms of the mid-level interconnect with the corresponding contact pads of the second substrate; and

actuating the first portion of the opposing arms with a load to activate a surface of the corresponding contact pads of the second substrate to provide a reusable surface mount attachment between the second substrate and the mid-level interconnect.

14. The method of claim 13 further comprising:

aligning a second portion of the opposing arms of the mid-level interconnect with the corresponding contact pads of the first substrate; and

actuating a second portion of the opposing arms with a load to activate a surface of the corresponding contact pads of the second substrate to provide a reusable surface mount attachment between the first substrate and the mid-level interconnect.

15. The method of claim 11 wherein:

releasing a load on the mid-level interconnect to disengage the first substrate from the mid-level interconnect;

replacing the first substrate with a patch including an attached chipset; and

actuating opposing arms of the mid-level interconnect to engage a respective surface of the contact pads of the patch to form an upgraded substrate assembly.

16. The method of claim 11 wherein:

the first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and

a surface area of the first substrate is smaller than surface area of the second substrate.

17. The method of claim 11 wherein:

the first substrate is a high density interconnect patch.

18. The method of claim 11 wherein:

the first substrate comprises a core having a thickness that is no greater than 37 micrometers.

19. The microelectronic package of claim 11 wherein the double-compression interconnect comprises:

one or more through-hole posts to provide a load to compress and actuate a double compression mid-level interconnect.

20. The method of claim 11, further comprising:

coupling first level interconnects having the first pitch at a first surface of the microelectronic die to the first level interconnects of the first surface of the first substrate; and

coupling first level interconnects having the third pitch at a first surface of the motherboard to the second level interconnects at the second surface of the second substrate.