Method of forming a field effect transistor

• US 8,440,515 B2
• Filed: 08/13/2008
• Issued: 05/14/2013
• Est. Priority Date: 08/15/2002
• Status: Active Grant

• Current Assignee: Michael P. Violette, Micron Technology, Inc., Robert Burke, Sanh D. Tang
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Sanh D., Violette, Michael P., Burke, Robert
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US12/191,119
• Publication Number:
  US 20080311719A1
• Time in Patent Office: 1,735 Days
• Field of Search: 438/197, 438/296, 438/643
• US Class Current: 438/197
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/0726 the arrangement including a circuit for tuning the resonance frequency of an antenna on the record carrier
• CPC Class Codes: G06K 19/07771 the record carrier comprising means for minimising adverse effects on the data communication capability of the record carrier, e.g. minimising Eddy currents induced in a proximate metal or otherwise electromagnetically interfering object
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.

Claims

1. A method of forming a field effect transistor having laterally spaced elevated source/drains on a substrate comprising:

forming and laterally spacing elevated source/drain material of the transistor prior to final patterning which defines the lateral peripheral outline of active area where such physically contacts field isolation and which defines the lateral peripheral outline of the field isolation where such physically contacts the active area;

forming conductive material of a gate of the transistor after forming the laterally spaced elevated source/drain material, and forming the conductive material of the gate and the elevated source/drain regions to have planar elevationally outermost surfaces that are coplanar; and

etching the conductive material of the gate and the elevated source/drain regions elevationally inward, and thereafter forming a conductor material onto each of the conductive material and elevated source/drains, the conductor material being of higher conductivity than the conductive material and the elevated source/drains.

2. The method of claim 1 comprising forming the field isolation to comprise trench isolation.

3. The method of claim 1 wherein the forming and laterally spacing of elevated source/drain material comprises depositing elevated source/drain material within openings formed in bulk monocrystalline semiconductive material.

4. The method of claim 3 comprising forming insulative material within the bulk monocrystalline semiconductive material openings prior to forming the elevated source/drain material within the bulk monocrystalline semiconductive material openings.

5. The method of claim 2 comprising forming the trench isolation material by at least two time spaced depositings.

6. The method of claim 1 comprising forming the laterally spaced elevated source/drain material against previously formed anisotropically etched spacers.

7. The method of claim 6 comprising removing the anisotropically etched spacers after forming the laterally spaced elevated source/drain material.

8. The method of claim 7 comprising removing the anisotropically etched spacers after the final patterning.

9. The method of claim 1 comprising after forming the laterally spaced elevated source/drain material, forming electrically insulative anisotropically etched spacers against sidewalls of the laterally spaced elevated source/drain material.

10. The method of claim 9 comprising after the final patterning, forming the electrically insulative anisotropically etched spacers against sidewalls of the laterally spaced elevated source/drain material.

11. The method of claim 1 comprising:

forming the laterally spaced elevated source/drain material against previously formed first anisotropically etched spacers;

removing the first anisotropically etched spacers after forming the laterally spaced elevated source/drain material; and

after removing the first anisotropically etched spacers, forming electrically insulative second anisotropically etched spacers against sidewalls of the laterally spaced elevated source/drain material.

12. The method of claim 1 comprising forming gate dielectric material of the gate of the transistor after forming the laterally spaced elevated source/drain material.

13. The method of claim 1 comprising forming LDD regions of the transistor prior to forming the gate dielectric material and the conductive material of the gate.

14. The method of claim 1 comprising forming LDD regions of the transistor prior to forming the laterally spaced elevated source/drain material.

15. The method of claim 1 comprising forming electrically insulative material upon which the laterally spaced elevated source/drain material is formed.

16. The method of claim 1 comprising forming the laterally spaced elevated source/drain material to comprise polysilicon.

17. The method of claim 16 wherein forming the laterally spaced elevated source/drain material comprises deposition of polysilicon followed by polishing an outermost surface thereof.

18. A method of forming a field effect transistor having laterally spaced elevated source/drains on a substrate comprising:

forming and laterally spacing elevated source/drain material of the transistor prior to final patterning which defines the lateral peripheral outline of active area where such physically contacts field isolation and which defines the lateral peripheral outline of the field isolation where such physically contacts the active area; and

after forming the laterally spaced elevated source/drain material, forming electrically insulative anisotropically etched spacers against sidewalls of the laterally spaced elevated source/drain material, the electrically insulative anisotropically etched spacers being of at least two different elevational thicknesses.