FinFET and method of fabricating the same

• US 8,440,517 B2
• Filed: 10/13/2010
• Issued: 05/14/2013
• Est. Priority Date: 10/13/2010
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Fu, Chu-Yun, Yang, Shu-Tine, Chen, Hung-Ming, Lin, Hung-Ta, Huang, Shin-Yeh
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US12/903,712
• Publication Number:
  US 20120091538A1
• Time in Patent Office: 944 Days
• Field of Search: 438149-151, 438/197, 438/212, 438/268, 438283-294, 438585-591, 438/795, 257/E21.224, 257/409, 257/27.062, 257/112, 257/29.255, 257/269
• US Class Current: 438/197
• CPC Class Codes: H01L 21/02293 formation of epitaxial layers by a deposition process epitaxial growth per se C30B
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7855 with at least two independent gates

Abstract

The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces; a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin comprises a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin comprises a non-recessed portion having a top surface higher than the tapered top surfaces; and a gate stack over the non-recessed portion of the fin.

Claims

1. A method of fabricating a fin field effect transistor (FinFET) comprising:

providing a substrate having a first insulation region and a second insulation region having respective top surfaces, and a fin between the first and second insulation regions, wherein the top surfaces of the first and second insulation regions are below a top surface of the fin;

forming a gate stack over a portion of the fin and over a portion of the first and second insulation regions;

recessing a portion of the fin not covered by the gate stack to form a recessed portion of the fin below the top surfaces of the first and second insulation regions;

etching corners of the top surfaces of the first and second insulation regions not covered by the gate stack to form tapered top surfaces of the first and second insulation regions; and

selectively growing a strained material over the recessed portion of the fin and the tapered top surfaces of the first and second insulation regions.

2. The method of claim 1, wherein the strained material is grown to have a substantially flat surface.

3. The method of claim 1, wherein the etching corners of the top surfaces of the first and second insulation regions not covered by the gate stack is performed using a wet etching process.

4. The method of claim 3, wherein the wet etching process comprises etching corners of the top surfaces of the first and second insulation regions not covered by the gate stack in a solution comprising HF.

5. The method of claim 1, wherein the etching corners of the top surfaces of the first and second insulation regions not covered by the gate stack is performed using a non-biased dry etching process.

6. The method of claim 5, wherein the non-biased dry etching process is performed using CHF₃ as etching gases.

7. The method of claim 5, wherein the non-biased dry etching process is performed using BF₃ as etching gases.

8. The method of claim 1, wherein the growing the strained material is performed by a low-pressure chemical vapor deposition (LPCVD).

9. A method of making a semiconductor structure, comprising:

forming a plurality of fin structures on a substrate;

forming a plurality of insulation structures, each pair of adjacent two of the insulation structures sandwiching a corresponding one of the fin structures, top surfaces of the insulation structures being lower than top surfaces of the fin structures;

partially recessing the fin structures to form a plurality of recessed portions of the fin structures, top surfaces of the recessed portions being lower than the top surfaces of the insulation structures, and the insulation structures and recessed portions of the fin structures defining a plurality of trenches;

partially removing corners of the top surfaces of the insulation structures to enlarge widths of top portions of the trenches; and

growing a strain-inducing structure filling the trenches, the strain-inducing structure having a top surface higher than the top surfaces of the insulation structures, and the strain-inducing structure being arranged to strain the plurality of fin structures.

10. The method of claim 9, wherein the partially removing corners of the top surfaces of the insulation structures is performed by a wet etching process using a solution comprising HF.

11. The method of claim 9, wherein the partially removing corners of the top surfaces of the insulation structures is performed by a non-biased dry etching process.

12. The method of claim 11, wherein the non-biased dry etching process is performed using CHF₃ or BF₃ as etching gases.

13. The method of claim 9, wherein the growing the strain-inducing structure is performed by a low-pressure chemical vapor deposition (LPCVD) process.

14. The method of claim 9, wherein the LPCVD process is performed at a temperature ranging from about 400°

C. to 800°

C. and under a pressure ranging from about 1 Torr to 200 Torr.

15. A method of making a semiconductor structure, comprising:

forming a plurality of insulation structures over a substrate;

forming a plurality of trenches, each of the plurality of trenches being between two corresponding insulation structures of the plurality of insulation structures, and the trenches exposing portions of the substrate;

shaping top portions of the insulation structures to have tapered top surfaces after the formation of the plurality of trenches; and

growing a silicon-containing structure on the exposed portions of substrate, the silicon-containing structure filling the trenches and covering the corresponding tapered top surfaces between the trenches.

16. The method of claim 15, wherein the shaping the top portions of the insulation structures is performed by a wet etching process using a solution comprising HF.

17. The method of claim 15, wherein the shaping the top portions of the insulation structures is performed by a non-biased dry etching process.

18. The method of claim 17, wherein the non-biased dry etching process is performed using CHF₃ or BF₃ as etching gases.

19. The method of claim 15, wherein the growing the silicon-containing structure is performed by a low-pressure chemical vapor deposition (LPCVD).

20. The method of claim 19, wherein the LPCVD is performed at a temperature ranging from about 400°

C. to 800°

C. and under a pressure ranging from about 1 Torr to 200 Torr.