Forming a phase change memory with an ovonic threshold switch

• US 8,440,535 B2
• Filed: 05/03/2012
• Issued: 05/14/2013
• Est. Priority Date: 10/28/2005
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC (Micron Technology, Inc.)
• Original Assignee: Ovonyx Incorporated (Micron Technology, Inc.)
• Inventors: Dennison, Charles H.
• Primary Examiner(s): Chang, Leonard
• Assistant Examiner(s): Seven, Evren
• Application Number:
  US13/463,072
• Publication Number:
  US 20120220099A1
• Time in Patent Office: 376 Days
• Field of Search: 438/381
• US Class Current: 438/381
• CPC Class Codes: H10B 63/24 of the Ovonic threshold switching type
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A phase change memory may include an ovonic threshold switch formed over an cyanic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.

Claims

1. A method comprising:

forming an ovonic threshold switch device including a chalcogenide layer and a plug wherein the chalcogenide layer overlaps the plug on two opposed sides;

forming an ovonic memory device directly underlying said ovonic threshold switch device; and

forming said ovonic memory device including a chalcogenide layer which is defined to have a dimension in common with said ovonic threshold switch device.

2. The method of claim 1 including forming a common electrode between said ovonic memory device and ovonic threshold switch device.

3. The method of claim 2 including etching a stack of layers to form said ovonic threshold switch device.

4. The method of claim 3 including etching said common electrode during the same etch used to etch said stack.

5. The method of claim 4 including etching said common electrode using the same mask used to etch said stack.

6. The method of claim 5 including using a hard mask to etch said stack.

7. The method of claim 1 including forming said ovonic memory including a pore having a chalcogenide layer and an electrode in said pore.

8. The method of claim 1 including forming said ovonic memory with a pore filled with an electrode.