Schemes for forming barrier layers for copper in interconnect structures

• US 8,440,564 B2
• Filed: 07/17/2012
• Issued: 05/14/2013
• Est. Priority Date: 11/21/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chen, Hai-Ching, Bao, Tien-I
• Primary Examiner(s): Sarkar, Asok K
• Application Number:
  US13/551,500
• Publication Number:
  US 20120282768A1
• Time in Patent Office: 301 Days
• Field of Search: 257/E21.199, 257/E21.584, 438/627, 438/630, 438/643, 438/664, 438/687
• US Class Current: 438/653
• CPC Class Codes: H01L 21/322 to modify their internal properties, e.g. to produce internal imperfections
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

Claims

1. A method of forming a semiconductor structure, the method comprising:

forming an opening into a low-k dielectric layer over a substrate, the opening extending from a top surface of the low-k dielectric layer into the low-k dielectric layer;

forming a first barrier layer lining the opening;

embedding a conductive wiring in a remaining portion of the opening;

removing oxygen from the conductive wiring; and

plating a second barrier layer to cover exposed portions of the conductive wiring and the first barrier layer, wherein the second barrier layer comprises substantially same materials as the first barrier layer.

2. The method of claim 1, wherein the first and the second barrier layers have greater than about 70 percent materials in common.

3. The method of claim 1, wherein the first and the second barrier layers comprise a material selected from the group consisting essentially of Ti, TiN, Ta, TaN, CoP, CoB, CoWP, CoWB, NiWP, CoSnP, NiWB, CuSi, ZrN, NiMoP, and combinations thereof.

4. The method of claim 1, wherein the first and the second barrier layers comprise a cobalt-containing material or a nickel-containing material.

5. The method of claim 1, wherein the plating the second barrier layer further comprises plating the second barrier layer at least in part through electroless plating.

6. The method of claim 1, wherein the second barrier layer comprises the same materials as the first barrier layer.

7. A method of forming a semiconductor structure, the method comprising:

depositing a low-k dielectric layer on an substrate;

patterning the low-k dielectric layer to form an opening, the opening comprising sidewalls and a bottom;

depositing a barrier layer along the sidewalls and the bottom of the opening;

filling the opening with a conductive material after the depositing the barrier layer;

treating the conductive material with a hydrogen-based gas environment; and

forming a cap layer over the barrier layer and the conductive material, wherein the cap layer and the barrier layer comprise substantially the same material and the cap layer does not extend over the low-k dielectric layer.

8. The method of claim 7, wherein the cap layer and the barrier layer have greater than about 70 percent materials in common.

9. The method of claim 7, wherein the cap layer and the barrier layer comprise a material selected from the group consisting essentially of Ti, TiN, Ta, TaN, CoP, CoB, CoWP, CoWB, NiWP, CoSnP, NiWB, CuSi, ZrN, NiMoP, and combinations thereof.

10. The method of claim 7, wherein the cap layer and the barrier layer comprise a cobalt-containing material or a nickel-containing material.

11. The method of claim 7, wherein the forming the cap layer further comprises plating the cap layer at least in part through electroless plating.

12. The method of claim 7, wherein the cap layer comprises the same materials as the barrier layer.

13. The method of claim 7, wherein the forming the cap layer comprises at least in part plating the cap layer.

14. The method of claim 7, wherein the conductive material has a planar top surface.

15. A method of forming a semiconductor structure, the method comprising:

lining an opening in a low-k dielectric layer with a first barrier material;

filling the opening with a conductive material, wherein the conductive material has a planar top surface after the filling the opening;

treating the conductive material with a nitrogen-based gas environment; and

plating a second barrier material onto exposed regions of the first barrier material and the conductive material, the second barrier material and the first barrier material being substantially the same material.

16. The method of claim 15, wherein the second barrier material is the same as the first barrier material.

17. The method of claim 15, wherein the first barrier material and the second barrier material have greater than about 70 percent materials in common.

18. The method of claim 15, wherein the first barrier material and the second barrier material comprise a material selected from the group consisting essentially of Ti, TiN, Ta, TaN, CoP, CoB, CoWP, CoWB, NiWP, CoSnP, NiWB, CuSi, ZrN, NiMoP, and combinations thereof.

19. The method of claim 15, wherein the first barrier material and the second barrier material comprise a cobalt-containing material or a nickel-containing material.

20. The method of claim 15, wherein the plating the second barrier material further comprises plating the second barrier material at least in part through electroless plating.