Semiconductor device and manufacturing method thereof

• US 8,441,009 B2
• Filed: 12/21/2010
• Issued: 05/14/2013
• Est. Priority Date: 12/25/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ieda, Yoshinori
• Primary Examiner(s): PERT, EVAN T
• Application Number:
  US12/974,254
• Publication Number:
  US 20110156023A1
• Time in Patent Office: 875 Days
• Field of Search: 257/43, 257/316, 257/E29.304, 257/E21.681, 438/104, 438/266
• US Class Current: 257/43
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region

Abstract

In a semiconductor device using a nonvolatile memory, high speed erasing operation and low power consumption are realized. In a nonvolatile memory in which a channel formation region, a tunnel insulating film, and a floating gate are stacked in this order, the channel formation region is formed using an oxide semiconductor layer. In addition, a metal wiring for erasing is provided in a lower side of the channel formation region so as to face the floating gate. With the above structure, when erasing operation is performed, charge accumulated in the floating gate is extracted to the metal wiring through the channel formation region. Consequently, high speed erasing operation and low power consumption of the semiconductor device can be realized.

Claims

1. A semiconductor device comprising:

a metal wiring;

an oxide semiconductor layer provided over and in contact with the metal wiring;

a first insulating film provided over the oxide semiconductor layer;

a floating gate provided over the first insulating film;

a second insulating film provided over the floating gate; and

a control gate provided over the second insulating film.

2. The semiconductor device according to claim 1, wherein an electron carrier concentration of the oxide semiconductor layer is less than 1×

10¹⁶ cm<sup>−

3</sup>.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer contains In and Zn.

4. The semiconductor device according to claim 1, wherein the metal wiring contains Al or Cu.

5. The semiconductor device according to claim 1, wherein a width of the metal wiring is larger than or equal to a width of the floating gate.

6. The semiconductor device according to claim 1, wherein the metal wiring is provided so as to overlap with the floating gate, and both edges of the metal wiring are aligned with or on an outer side than both edges of the floating gate.

7. The semiconductor device according to claim 1, wherein a width of the metal wiring is smaller than a width of the floating gate.

8. The semiconductor device according to claim 1, wherein the metal wiring is provided so as to overlap with the floating gate, and both edges of the metal wiring are on an inner side than the both edges of the floating gate.

9. A semiconductor device comprising:

a control gate;

a first insulating film provided over the control gate;

a floating gate provided over the first insulating film;

a second insulating film provided over the floating gate;

an oxide semiconductor layer provided over the second insulating film; and

a metal wiring provided over and in contact with the oxide semiconductor layer.

10. The semiconductor device according to claim 9, wherein an electron carrier concentration of the oxide semiconductor layer is less than 1×

10¹⁶ cm<sup>−

3</sup>.

11. The semiconductor device according to claim 9, wherein the oxide semiconductor layer contains In and Zn.

12. The semiconductor device according to claim 9, wherein the metal wiring contains Al or Cu.

13. The semiconductor device according to claim 9, wherein a width of the metal wiring is larger than or equal to a width of the floating gate.

14. The semiconductor device according to claim 9, wherein the metal wiring is provided so as to overlap with the floating gate, and both edges of the metal wiring are aligned with or on an outer side than both edges of the floating gate.

15. The semiconductor device according to claim 9, wherein a width of the metal wiring is smaller than a width of the floating gate.

16. The semiconductor device according to claim 9, wherein the metal wiring is provided so as to overlap with the floating gate, and both edges of the metal wiring are on an inner side than the both edges of the floating gate.

17. A method for manufacturing a semiconductor device comprising the steps of:

forming a metal wiring;

forming an oxide semiconductor layer over the metal wiring;

forming a first insulating film over the oxide semiconductor layer;

forming a floating gate over the first insulating film;

forming a second insulating film over the floating gate; and

forming a control gate over the second insulating film.

18. The method for manufacturing a semiconductor device, according to claim 17, wherein an electron carrier concentration of the oxide semiconductor layer is less than 1×

10¹⁶ cm<sup>−

3</sup>.

19. The method for manufacturing a semiconductor device, according to claim 17, wherein the oxide semiconductor layer contains In and Ga.

20. The method for manufacturing a semiconductor device, according to claim 17, wherein the metal wiring contains Al or Cu.

21. The method for manufacturing a semiconductor device, according to claim 17, wherein a width of the metal wiring is larger than or equal to a width of the floating gate.

22. The method for manufacturing a semiconductor device, according to claim 17, wherein the metal wiring is provided so as to overlap with the floating gate, and both edges of the metal wiring are aligned with or on an outer side than both edges of the floating gate.

23. The method for manufacturing a semiconductor device, according to claim 17, wherein a width of the metal wiring is smaller than a width of the floating gate.

24. The method for manufacturing a semiconductor device, according to claim 17, wherein the metal wiring is provided so as to overlap with the floating gate, and both edges of the metal wiring are on an inner side than both edges of the floating gate.

25. A method for manufacturing a semiconductor device comprising the steps of:

forming a control gate;

forming a first insulating film over the control gate;

forming a floating gate over the first insulating film;

forming a second insulating film over the floating gate;

forming an oxide semiconductor layer over the second insulating film; and

forming a metal wiring over the oxide semiconductor layer.

26. The method for manufacturing a semiconductor device, according to claim 25, wherein an electron carrier concentration of the oxide semiconductor layer is less than 1×

10¹⁶ cm<sup>−

3</sup>.

27. The method for manufacturing a semiconductor device, according to claim 25, wherein the oxide semiconductor layer contains In and Ga.

28. The method for manufacturing a semiconductor device, according to claim 25, wherein the metal wiring contains Al or Cu.

29. The method for manufacturing a semiconductor device, according to claim 25, wherein a width of the metal wiring is larger than or equal to a width of the floating gate.

30. The method for manufacturing a semiconductor device, according to claim 25, wherein the metal wiring is provided so as to overlap with the floating gate, and both edges of the metal wiring are aligned with or on an outer side than both edges of the floating gate.

31. The method for manufacturing a semiconductor device, according to claim 25, wherein a width of the metal wiring is smaller than a width of the floating gate.

32. The method for manufacturing a semiconductor device, according to claim 25, wherein the metal wiring is provided so as to overlap with the floating gate, and both edges of the metal wiring are on an inner side than both edges of the floating gate.