Semiconductor device and manufacturing method of the same

• US 8,441,065 B2
• Filed: 08/05/2010
• Issued: 05/14/2013
• Est. Priority Date: 12/16/2005
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Suzuki, Hirokatsu, Fujiki, Atsushi, Nakazawa, Yoshito
• Primary Examiner(s): Quach, Tuan N.
• Application Number:
  US12/851,101
• Publication Number:
  US 20100315751A1
• Time in Patent Office: 1,013 Days
• Field of Search: 257/330, 257/341, 257355-358, 257/360, 257/E29.255, 257/E29.26
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device which combines reliability and the guarantee of electrical characteristics is provided. A power MOSFET and a protection circuit formed over the same semiconductor substrate are provided. The power MOSFET is a trench gate vertical type P-channel MOSFET and the conduction type of the gate electrode is assumed to be P-type. The protection circuit includes a planar gate horizontal type offset P-channel MOSFET and the conduction type of the gate electrode is assumed to be N-type. These gate electrode and gate electrode are formed in separate steps.

Claims

1. A semiconductor device for use in an automobile, including:

a semiconductor substrate;

a P-channel trench gate MOSFET having a gate electrode, a source and a drain, disposed over a main surface of the semiconductor substrate; and

a protection circuit coupled to the gate electrode of the P-channel trench gate MOSFET,

the protection circuit comprising a P-channel planar gate MOSFET disposed over the main surface of the semiconductor substrate,

wherein a conduction type of the gate electrode of the P-channel trench gate MOSFET is P-type,

wherein a conduction type of a gate electrode of the P-channel planar gate MOSFET is n-type,

wherein the source of the P-channel trench gate MOSFET is coupled to a battery in the automobile,

wherein the drain of the P-channel trench gate MOSFET is coupled to a load in the automobile,

wherein the load is coupled to a ground terminal in the automobile.

2. The semiconductor device according to claim 1,

wherein the P-channel planar gate MOSFET has an offset drain structure.

3. The semiconductor device according to claim 1,

wherein the protection circuit is a temperature detection overheat cutoff circuit.

4. The semiconductor device according to claim 1,

wherein the protection circuit is an over-current limit circuit.

5. A semiconductor device comprising:

a semiconductor substrate;

a P-channel trench gate MOSFET disposed over a main surface of the semiconductor substrate and having a gate electrode, a source and a drain, the gate electrode of the P-channel trench gate MOSFET is P-type polycrystalline silicon; and

a protection circuit coupled to the gate electrode of the P-channel trench gate MOSFET and disposed over the main surface of the semiconductor substrate, the protection circuit including a P-channel planar gate MOSFET whose gate electrode is N-type polycrystalline silicon.

6. The semiconductor device according to claim 5,

wherein the P-channel planar gate MOSFET has an offset drain structure.

7. The semiconductor device according to claim 5,

wherein the protection circuit includes a temperature detection overheat cutoff circuit or an over-current limit circuit.

8. The semiconductor device according to claim 5,

wherein the P-type polycrystalline silicon is doped with boron (B), and

wherein the N-type polycrystalline silicon is doped with arsenic (As) or phosphorus (P).

9. A semiconductor device comprising:

a gate terminal;

a source terminal;

a drain terminal;

a semiconductor substrate;

a P-channel trench gate MOSFET disposed over a main surface of the semiconductor substrate and having a gate electrode coupled to the gate terminal, a source coupled to the source terminal and a drain coupled to the drain terminal, the gate electrode of the P-channel trench gate MOSFET is P-type polycrystalline silicon; and

a protection circuit disposed over the main surface of the semiconductor substrate and coupled between the gate terminal and the source terminal, the protection circuit including a P-channel planar gate MOSFET having a gate electrode of N-type polycrystalline silicon.

10. The semiconductor device according to claim 9,

wherein the P-channel planar gate MOSFET has an offset drain structure.

11. The semiconductor device according to claim 9,

wherein the protection circuit includes a temperature detection overheat cutoff circuit or an over-current limit circuit.

12. The semiconductor device according to claim 9,

wherein the P-type polycrystalline silicon includes boron (B), and

wherein the N-type polycrystalline silicon includes arsenic (As) or phosphorus (P).

13. A semiconductor device comprising:

a gate terminal;

a source terminal;

a drain terminal;

a semiconductor substrate;

a P-channel trench gate MOSFET disposed over a main surface of the semiconductor substrate and having a gate electrode coupled to the gate terminal, a source coupled to the source terminal and a drain coupled to the drain terminal, the gate electrode of the P-channel trench gate MOSFET is boron (B) doped P-type polycrystalline silicon; and

a protection circuit for a temperature detection overheat cutoff circuit or an over-current limit circuit, the protection circuit being disposed over the main surface of the semiconductor substrate and coupled between the gate terminal and the source terminal, the protection circuit including a P-channel planar gate MOSFET with an offset drain structure having a gate electrode of arsenic (As) or phosphorus (P) doped N-type polycrystalline silicon.