Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package

• US 8,441,110 B1
• Filed: 05/17/2011
• Issued: 05/14/2013
• Est. Priority Date: 06/21/2006
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Choi, Yeon Ho
• Primary Examiner(s): Parekh, Nitin
• Application Number:
  US13/109,845
• Time in Patent Office: 728 Days
• Field of Search: 257/666, 257/784, 257/E23.031, 257/E23.051
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48108 the connector not being orthogonal to a side surface of the semiconductor or solid-state body, e.g. fanned-out connectors, radial layout
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48253 connecting the wire to a potential ring of the item
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49173 Radial fan-out arrangements
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49551 characterised by bent parts
• CPC Class Codes: H01L 23/49558 Insulating layers on lead frames, e.g. bridging members
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body.

Claims

1. A semiconductor package comprising:

a generally planar die paddle defining opposed top and bottom paddle surfaces and multiple peripheral edge segments;

a plurality of first leads which each define opposed top and bottom lead surfaces and each including a downset connected thereto, the first leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle;

a plurality of second leads segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle;

a semiconductor die attached to the top paddle surface of the die paddle and electrically connected to at least one of each of the first and second leads; and

a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first and second leads and the semiconductor die such that the downsets connected to each of the first leads are covered by the package body, at least portions of the bottom paddle surface of the die paddle and the bottom lead surfaces of the first leads are exposed in and substantially coplanar with the bottom surface of the package body, and portions of the second leads protrude from respective ones of the side surfaces of the package body.

2. The semiconductor package of claim 1 wherein the semiconductor die is electrically connected to the first and second leads by conductive wires which are covered by the package body.

3. The semiconductor package of claim 1 wherein the die paddle has a generally quadrangular configuration, and the first and second leads are segregated into at least four sets which each extend along a respective one of the peripheral edge segments of the die paddle.

4. The semiconductor package of claim 3 wherein:

each of the first leads includes a pad portion which is exposed in the bottom surface of the package body and a tie bar portion which protrudes from the pad portion and includes the downset formed therein; and

the tie bar portion of each of the first leads of each set thereof extends between an adjacent pair of the second leads of a corresponding set thereof.

5. The semiconductor package of claim 4 wherein:

the die paddle and the pad portions of the first leads extend along a first plane; and

portions of the tie bar portions of the first leads and portions of the second leads each extend along a second plane which is disposed in spaced, generally parallel relation to the first plane.

6. The semiconductor package of claim 1 wherein at least some of the second leads are formed to include an inner end portion which is angled toward the die paddle.

7. The semiconductor package of claim 1 wherein each set of the first leads are separated from a corresponding one of the peripheral edge segments of the die paddle by an elongate groove which is formed in the bottom surface of the package body.

8. A semiconductor package comprising:

a generally planar die paddle defining opposed top and bottom paddle surfaces and multiple peripheral edge segments;

a plurality of first leads which each include a pad portion defining opposed top and bottom pad surfaces and each including a downset connected thereto, the first leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle in electrical isolation from the die paddle and each other;

a plurality of second leads which each define opposed top and bottom second lead surfaces, the second leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle in electrical isolation from the die paddle, the first leads, and each other;

a semiconductor die attached to the top paddle surface of the die paddle and electrically connected to at least one of each of the first and second leads; and

a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first and second leads and the semiconductor die such that the downsets connected to each of the first leads are covered by the package body, at least portions of the bottom paddle surface of the die paddle and the bottom pad surfaces of the first leads are exposed in and substantially coplanar with the bottom surface of the package body, and portions of the second leads protrude from respective ones of the side surfaces of the package body.

9. The semiconductor package of claim 8 wherein the semiconductor die is electrically connected to the first and second leads by conductive wires which are covered by the package body.

10. The semiconductor package of claim 8 wherein the die paddle has a generally quadrangular configuration, and the first and second leads are segregated into at least four sets which each extend along a respective one of the peripheral edge segments of the die paddle.

11. The semiconductor package of claim 8 wherein each of the first leads further includes a tie bar portion which protrudes from the pad portion and includes a downset which is formed therein and covered by the package body.

12. The semiconductor package of claim 11 wherein:

the die paddle and the pad portions of the first leads extend along a first plane; and

the second leads and portions of the tie bar portions of the first leads each extend along a second plane which is disposed in spaced, generally parallel relation to the first plane.

13. The semiconductor package of claim 8 wherein at least some of the second leads are formed to include an inner end portion which is angled toward the die paddle.

14. The semiconductor package of claim 8 wherein the pad portions of each set of the first leads are separated from a corresponding one of the peripheral edge segments of the die paddle by an elongate groove which is formed in the bottom surface of the package body.

15. A semiconductor package comprising:

a generally planar die paddle defining opposed top and bottom paddle surfaces;

a plurality of first leads which each define opposed top and bottom lead surfaces and each includes a downset connected thereto, the first leads at least partially circumventing the die paddle in spaced relation thereto;

a plurality of second leads at least partially circumventing the die paddle in spaced relation thereto, wherein at least some of the second leads are formed to include an inner end portion which is angled toward the die pad;

a semiconductor die attached to the top paddle surface of the die paddle and electrically connected to at least one of each of the first and second leads; and

a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first and second leads and the semiconductor die such that the downsets connected to each of the first leads are covered by the package body, at least portions of the bottom paddle surface of the die paddle and the bottom lead surfaces of the first leads are exposed in and substantially coplanar with the bottom surface of the package body, and portions of the second leads protrude from respective ones of the side surfaces of the package body.

16. The semiconductor package of claim 15 wherein the semiconductor die is electrically connected to the first and second leads by conductive wires which are covered by the package body.

17. The semiconductor package of claim 15 wherein the die paddle has a generally quadrangular configuration, and the first and second leads are segregated into at least four sets which each extend along a respective one of the peripheral edge segments of the die paddle.

18. The semiconductor package of claim 15 wherein:

each of the first leads includes a pad portion which is exposed in the bottom surface of the package body and a tie bar portion which protrudes from the pad portion and includes the downset formed therein; and

the tie bar portion of each of the first leads of each set thereof extends between an adjacent pair of the second leads of a corresponding set thereof.

19. The semiconductor package of claim 18 wherein:

the die paddle and the pad portions of the first leads extend along a first plane; and

portions of the tie bar portions of the first leads and portions of the second leads each extend along a second plane which is disposed in spaced, generally parallel relation to the first plane.

20. The semiconductor package of claim 15 wherein each set of the first leads are separated from a corresponding one of the peripheral edge segments of the die paddle by an elongate groove which is formed in the bottom surface of the package body.