Protection layer for adhesive material at wafer edge

• US 8,441,136 B2
• Filed: 07/27/2012
• Issued: 05/14/2013
• Est. Priority Date: 09/14/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiou, Wen-Chih, Wu, Weng-Jin, Shue, Shau-Lin
• Primary Examiner(s): Wagner, Jenny L
• Application Number:
  US13/560,200
• Publication Number:
  US 20120292783A1
• Time in Patent Office: 291 Days
• Field of Search: 257/787, 257/790
• US Class Current: 257/790
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/81001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01327 Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

This description relates to a semiconductor device including a wafer having a first surface and a second surface opposite to the first surface and a carrier attached to the first surface of the wafer by an adhesive layer, a portion of the adhesive layer adjacent to an edge of the wafer is exposed. The semiconductor device further includes a protection layer to cover the exposed portion of the adhesive layer. The semiconductor device further includes a plurality of dies attached to the second surface and a molding compound encapsulating the plurality of dies.

Claims

1. A semiconductor device, comprising:

a wafer having a first surface and a second surface opposite to the first surface;

a carrier attached to the first surface of the wafer by an adhesive layer, a portion of the adhesive layer adjacent to an edge of the wafer is exposed;

a protection layer to cover the exposed portion of the adhesive layer;

a plurality of dies attached to the second surface; and

a molding compound encapsulating the plurality of dies.

2. The semiconductor device of claim 1, wherein the protection layer covers a portion of the carrier.

3. The semiconductor device of claim 1, wherein the protection layer covers the second surface of the wafer.

4. The semiconductor device of claim 1, wherein the protection layer covers an edge of the wafer and exposes at least a portion of the second surface of the wafer.

5. The semiconductor device of claim 1, wherein the protection layer comprises at least one of an oxide film, a nitride film, a carbide film, a polymer-based material, a resin-based material, polyimide, or a spin-on material.

6. The semiconductor device of claim 1, wherein the molding compound comprises at least one of a polymer-based material, a resin-based material, silicon oxide, an epoxy, or benzocyclobutene.

7. The semiconductor device of claim 1, wherein the plurality of dies comprises at least one of a memory chip, a radio frequency chip, or a logic chip.

8. A semiconductor device, comprising:

a wafer having a first surface and a second surface opposite to the first surface;

a carrier attached to the first surface of the wafer by an adhesive layer;

a protection layer over any portion of the adhesive layer exposed by the wafer and the carrier;

a plurality of dies attached to the second surface of the wafer; and

a molding compound encapsulating the plurality of dies.

9. The semiconductor device of claim 8, wherein the protection layer covers a portion of the carrier.

10. The semiconductor device of claim 8, wherein the protection layer covers the second surface of the wafer.

11. The semiconductor device of claim 8, wherein the protection layer covers an edge of the wafer and exposes at least a portion of the second surface of the wafer.

12. The semiconductor device of claim 8, wherein the protection layer comprises at least one of an oxide film, a nitride film, a carbide film, a polymer-based material, a resin-based material, polyimide, or a spin-on material.

13. The semiconductor device of claim 8, wherein the molding compound comprises at least one of a polymer-based material, a resin-based material, silicon oxide, an epoxy, or benzocyclobutene.

14. The semiconductor device of claim 8, wherein the plurality of dies comprises at least one of a memory chip, a radio frequency chip, or a logic chip.