High-frequency switch circuit
First Claim
1. A high-frequency switch circuit comprising:
- a first switch that is connected between a common terminal and a first terminal; and
a second switch that is connected between the common terminal and a second terminal,wherein each of the first and second switches includes a plurality of field-effect transistors connected in series and each having a body, a source, a drain, and a gate,a compensation capacitance that compensates a parasitic capacitance generated when the first switch is in an off-state is formed between the drain and the body or between the source and the body in at least one of the plurality of field-effect transistors of the first switch, anda compensation capacitance that compensates a parasitic capacitance generated when the second switch is in an off-state is formed between the drain and the body or between the source and the body in at least one of the plurality of field-effect transistors of the second switch.
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Accused Products
Abstract
A high-frequency switch circuit according to the present invention includes at least a first switch connected between a common terminal and a first terminal, and a second switch connected between the common terminal and a second terminal. Each of the first and second switches includes a plurality of field-effect transistors connected in series and each having a body, a source, a drain, and a gate. A compensation capacitance that compensates a parasitic capacitance generated when the first switch is in an off-state is formed between the drain and the body or between the source and the body in the FET of the first switch. A compensation capacitance that compensates a parasitic capacitance generated when the second switch is in an off-state is formed between the drain and the body or between the source and the body in the FET of the second switch.
26 Citations
17 Claims
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1. A high-frequency switch circuit comprising:
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a first switch that is connected between a common terminal and a first terminal; and a second switch that is connected between the common terminal and a second terminal, wherein each of the first and second switches includes a plurality of field-effect transistors connected in series and each having a body, a source, a drain, and a gate, a compensation capacitance that compensates a parasitic capacitance generated when the first switch is in an off-state is formed between the drain and the body or between the source and the body in at least one of the plurality of field-effect transistors of the first switch, and a compensation capacitance that compensates a parasitic capacitance generated when the second switch is in an off-state is formed between the drain and the body or between the source and the body in at least one of the plurality of field-effect transistors of the second switch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A high-frequency switch circuit comprising:
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a first switch that is connected between a common terminal and a first terminal; and a second switch that is connected between the common terminal and a second terminal, wherein each of the first and second switches includes a plurality of field-effect transistors connected in series and each having a body, a source, a drain, and a gate, a compensation capacitance that compensates a parasitic capacitance generated when the first switch is in an off-state is formed between the drain and the body or between the source and the body in at least one of the plurality of field-effect transistors of the first switch, and a compensation capacitance that compensates a parasitic capacitance generated when the second switch is in an off-state is formed between the drain and the body or between the source and the body in at least one of the plurality of field-effect transistors of the second switch, wherein a unit device of the field-effect transistors is a multi-finger type field-effect transistor that includes a plurality of body regions, a plurality of source and drain electrodes arranged on both sides of the plurality of body regions, a plurality of gate insulators respectively arranged on the plurality of body regions, and a plurality of gate electrodes respectively arranged on the plurality of gate insulators. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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Specification