Isolator with complementary configurable memory

• US 8,441,325 B2
• Filed: 06/30/2009
• Issued: 05/14/2013
• Est. Priority Date: 06/03/2004
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Dong, Zhiwei, Thomsen, Axel, Dupuis, Timothy, Leung, Ka Y., Alfano, Donald E., Callahan, Phil A., Javed, Ahsan
• Primary Examiner(s): Takaoka, Dean O
• Assistant Examiner(s): Wong, Alan
• Application Number:
  US12/494,618
• Publication Number:
  US 20100052826A1
• Time in Patent Office: 1,414 Days
• Field of Search: 333/1, 333/24.R, 375/258, 455/292, 455/333
• US Class Current: 333/24.R
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H04B 2203/5491 : using filtering and bypassing

Abstract

An isolator that includes first and second substantially identical circuitry galvanically isolated from each other and each having at least one communications channel thereon for communicating signals across an isolation boundary therebetween and each of said first and second circuitry having configurable functionality associated with the operation thereof. A coupling device is provided for coupling signal across the isolation boundary between the at least one communication channels of the first and second circuitry. First and second configuration memories are provided, each associated with a respective one of the first and second circuitry. First and second configuration control devices are provided, each associated with a respective one of the first and second circuitry and each configuring the functionality of the associated one of the first and second circuitry. The first and second configurable memories have stored therein complementary configuration information to control each of the functionalities of the first and second circuitry to operate in a complementary manner for communication of signals across the isolation boundary.

Claims

1. An isolator, comprising:

first and second substantially identical circuitry galvanically isolated from each other and each having at least one communications channel thereon for communicating signals across an isolation boundary therebetween and each of said first and second circuitry having configurable functionality associated with the operation thereof;

a coupling device coupling signal across said isolation boundary between said at least one communication channels of said first and second circuitry;

first and second configuration memories, each associated with a respective one of said first and second circuitry;

first and second configuration control devices, each associated with a respective one of said first and second circuitry and each configuring the functionality of the associated one of said first and second circuitry; and

said first and second configurable memories having stored therein complementary configuration information to control each of the functionalities of said first and second circuitry to operate in a complementary manner for communication of signals across said isolation boundary.

2. The isolator of claim 1, wherein said first and second circuitry are disposed on first and second respective and substantially identical integrated circuits, each in association with said associated configuration memories and said associated configuration control devices.

3. The isolator of claim 2, and further comprising an integrated circuit package having first and second galvanically isolated sides and associated signal pins for each of said sides and for containing in each of said sides a respective one of said first and second integrated circuits and said coupling device, and said respective configuration device adaptable to interface said at least one communication channel with at least one of said signal pins to allow signal to be transmitted from one of said signal pins on one side of said isolation boundary to one of said signal pins on the opposite side thereof.

4. The isolator of claim 3, wherein each of said first and second integrated circuits are powered independently.

5. The isolator of claim 1, wherein the configurable functionality is associated with the operation of the associated communication channel.

6. The isolator of claim 1, wherein the configurable functionality is independent of the operation of the associated communication channel.

7. The isolator of claim 1, wherein each of the first and second circuitry has multiple transmission channels for coupling signals across said isolation boundary and each of said multiple communication channels on one of said first and second circuitry associated with a complementary one of said communication channels on the other of said first and second circuitry via an associated coupling device coupling signal across said isolation boundary to form a complementary pair.

8. The isolator of claim 7, wherein said configuration control device is operable to configure at least two of said complementary pairs of communication channels to provide a data path in accordance with a particular serial data protocol and interface with one of said signal pins on one side of said integrated circuit package and a complementary one of said signal pins on the other side thereof.

9. The isolator of claim 8, wherein said configuration control device is operable to configure at least another one of said complementary pair of communication channels to define a timing function for said particular serial data protocol and associated with one of said signal pins on one side of said integrated circuit package and a complementary one of said signal pins on the other side thereof to transmit timing information across said isolation boundary.

10. The isolator of claim 7, wherein said configuration control device is operable to configure at least one of said complementary pair of communication channels to define a particular serial data protocol.

11. The isolator of claim 7, wherein said first and second circuitry are disposed on first and second respective and substantially identical integrated circuits, each in association with said associated configuration memories and said associated configuration control devices, each of said first and second integrated circuits disposed in an integrated circuit package on respective first and second galvanically isolated sides thereof and said integrated circuit package having associated signal pins for each of said sides wherein, on each of said first and second integrated circuits, there is included:

a plurality of I/O bond pads adaptable to be bonded to select ones of said associated signal pins complementary to said signal pins on the other of said sides of said integrated circuit package;

each of said coupling devices comprised of a reactive device disposed on said associated first or second integrated circuit and interfaced with one side of the associated one of said communication channels and having a bond pad interface associated therewith and a bond wire for connection with said reactive device associated with the complementary one of said communication channels on the other of said first and second integrated circuits;

each of said communication channels configurable to be connected on the other side thereof to a select one of said I/O bond pads;

wherein select ones of said communication channels are configured such that a signal input on one of said signal pins on one side of said integrated circuit package is transmitted across said isolation barrier to be output on the other side thereof on the complementary one of said signal pins.

12. The isolator of claim 11, wherein said reactive device comprises a capacitor.

13. The isolator of claim 1, wherein said first and second memories are substantially identical.

14. The isolator of claim 1, where said first and second memories are programmable memories.

15. The isolator of claim 14, wherein said first and second memories are One Time Programmable (OTP) memories.

16. A method comprising:

storing first configuration information in a first memory to configure a first communication interface to communicate over a galvanic isolation boundary;

storing second configuration information in a second memory separate from the first memory to configure a second communication interface to communicate with the first communication interface over the isolation boundary, wherein

the storing of the first and second configuration information is performed to configure the first and second communication interfaces to operate in a complimentary manner for communication of signals across the isolation boundary.

17. The method of claim 16, further comprising locating the first and second communication interfaces on separate integrated circuits separated by the isolation boundary.

18. The method of claim 16, further comprising adapting the first communication interface to communicate a signal from a pin associated with the first communication interface such that the signal is received by a pin associated with the second communication interface.

19. The method of claim 16, wherein storing the first configuration information comprises storing the first configuration communication in a one time programmable memory.

20. The method of claim 16, wherein storing the first information and storing the second information comprises storing the first information and the second information in substantially identical memories.