Memory device having memory cells with enhanced low voltage write capability
First Claim
1. A memory device comprising:
- a memory array comprising a plurality of memory cells;
at least a given one of the memory cells comprising;
a pair of cross-coupled inverters; and
write assist circuitry;
the write assist circuitry comprising;
first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell; and
second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell;
wherein each of the first and second switching circuitry comprise at least first, second and third write assist transistors;
wherein the first, second and third write assist transistors of the first switching circuitry are controlled using a common control signal, a worldline and a complemented bitline of the memory device, respectively, and the first, second and third write assist transistors of the second switching circuitry are controlled using the common control signal, the wordline and an uncomplemented bitline of the memory device, respectively; and
wherein the first and second switching circuitry are separately controlled such that during a write operation of the memory cell the supply node of one of the devices is connected to the supply node of the memory cell while the supply node of the other device is not connected to the supply node of the memory cell but is instead permitted to float.
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Accused Products
Abstract
A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled such that during a write operation of the memory cell the supply node of one of the devices is connected to the supply node of the memory cell while the supply node of the other device is not connected to the supply node of the memory cell but is instead permitted to float.
26 Citations
20 Claims
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1. A memory device comprising:
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a memory array comprising a plurality of memory cells; at least a given one of the memory cells comprising; a pair of cross-coupled inverters; and write assist circuitry; the write assist circuitry comprising; first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell; and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell; wherein each of the first and second switching circuitry comprise at least first, second and third write assist transistors; wherein the first, second and third write assist transistors of the first switching circuitry are controlled using a common control signal, a worldline and a complemented bitline of the memory device, respectively, and the first, second and third write assist transistors of the second switching circuitry are controlled using the common control signal, the wordline and an uncomplemented bitline of the memory device, respectively; and wherein the first and second switching circuitry are separately controlled such that during a write operation of the memory cell the supply node of one of the devices is connected to the supply node of the memory cell while the supply node of the other device is not connected to the supply node of the memory cell but is instead permitted to float. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A memory cell comprising:
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a pair of cross-coupled inverters; and write assist circuitry; the write assist circuitry comprising; first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell; and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell; wherein each of the first and second switching circuitry comprise at least first, second and third write assist transistors; wherein the first, second and third write assist transistors of the first switching circuitry are controlled using a common control signal, a wordline and a complemented bitline of a memory device, respectively, and the first, second and third write assist transistors of the second switching circuitry are controlled using the common control signal, the wordline and an uncomplemented bitline of the memory device, respectively; and wherein the first and second switching circuitry are separately controlled such that during a write operation of the memory cell the supply node of one of the devices is connected to the supply node of the memory cell while the supply node of the other device is not connected to the supply node of the memory cell but is instead permitted to float. - View Dependent Claims (17)
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18. A method comprising:
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providing a memory cell comprising a pair of cross-coupled inverters and associated write assist circuitry, the write assist circuitry comprising first and second switching circuitry, each switching circuitry comprising at least first, second and third write assist transistors; and during a write operation of the memory cell, configuring the write assist circuitry to connect a supply node of a device of one of the inverters to a supply node of the memory cell, by turning on at least one of the first, second and third write assist transistors of one of the first switching circuitry and the second switching circuitry while a supply node of a device of another one of the inverters is not connected to the supply node of the memory cell but is instead permitted to float, by turning off the first, second and third write assist transistors of the other one of the first switching circuitry and the second switching circuitry; wherein the first, second and third write assist transistors of the first switching circuitry are controlled using a common control signal, a wordline and a complemented bitline of a memory device, respectively, and the first, second and third write assist transistors of the second switching circuitry are controlled using the common control signal, the wordline and an uncomplemented bitline of the memory device, respectively. - View Dependent Claims (19, 20)
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Specification