Method for writing in a MRAM-based memory device with reduced power consumption

• US 8,441,844 B2
• Filed: 06/08/2011
• Issued: 05/14/2013
• Est. Priority Date: 07/07/2010
• Status: Active Grant

• Current Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Original Assignee: Crocus Technology S.A. (Sanken Electric Company Limited)
• Inventors: El Baraji, Mourad, Berger, Neal
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US13/155,669
• Publication Number:
  US 20120008380A1
• Time in Patent Office: 706 Days
• Field of Search: 365/48, 365/55, 365/62, 365/66, 365/74, 365/78, 365 80- 93, 365/100, 365/130, 365/131, 365/148, 365/158, 365171-173, 365/209, 365/213, 365/225.5, 365/230.07, 365/232, 365/243.5, 216/22, 257/295, 257/421, 257/422, 257/427, 257/E21.665, 257/E27.006, 438/3, 428810-816, 428817-8251, 428/826, 977933-935
• US Class Current: 365/158
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A method of writing in a memory device comprising a plurality of MRAM cells, each cell including a magnetic tunnel junction having a resistance that can be varied during a write operation when heated at a high threshold temperature; a plurality of word lines connecting cells along a row; and a plurality of bit lines connecting cells along a column; the method comprising supplying a bit line voltage to one of the bit lines and a word line voltage to one of the word lines for passing a heating current through the magnetic tunnel junction of a selected cell; said word line voltage is a word line overdrive voltage being higher than the core operating voltage of the cells such that the heating current has a magnitude that is high enough for heating the magnetic tunnel junction at the predetermined high threshold temperature. The memory device can be written with low power consumption.

Claims

1. A method of writing in a memory device comprising a plurality of magnetoresistive random access memory (MRAM) cells arranged in rows and columns, each MRAM cell to be written by using a thermally-assisted switching (TAS) write operation, including a magnetic tunnel junction having a resistance that can be varied during a write operation when the magnetic tunnel junction is heated at a high threshold temperature, and a select transistor electrically coupled to the magnetic tunnel junction;

a plurality of word lines connecting MRAM cells along a row; and

a plurality of bit lines connecting MRAM cells along a column;

comprising, during the write operation;

supplying a bit line voltage to one of the bit lines and a word line voltage to one of the word lines for passing a heating current through the magnetic tunnel junction of a selected MRAM cell;

once the magnetic tunnel junction has reached the high threshold temperature, varying the resistance of the magnetic tunnel junction; and

cooling the magnetic tunnel junction such as to freeze said resistance in its written value;

said word line voltage is a word line overdrive voltage being higher than the core operating voltage of the MRAM cells such that the heating current has a magnitude that is high enough for heating the magnetic tunnel junction at the predetermined high threshold temperature.

2. The method according to claim 1, wherein the word line overdrive voltage is a voltage pulse with a pulse duration being equal to or smaller than about 15 ns.

3. The method according to claim 1, wherein the word line overdrive voltage is generated by a charge pump or by a regulable external voltage provided by an input-output port.

4. The method according to claim 1, wherein the memory device further comprises a sense amplifier circuitry, and wherein the pulse duration of the word line overdrive voltage is controlled by the sense amplifier circuitry.

5. The method according to claim 1, wherein the select transistor is a high power transistor having a low threshold voltage.

6. The method according to claim 1, wherein the memory device further comprises a plurality of source lines connecting MRAM cells along a row, via the drain of their respective select transistor, and wherein the method further comprises supplying a source line overdrive voltage to the source line.

7. The method according to claim 6, wherein the source line overdrive voltage has a value substantially equal to the threshold voltage of the select transistor.

8. The method according to claim 6, further comprising a read operation including measuring the resistance of the magnetic tunnel junction, and supplying the source line overdrive voltage to the source line.