Strings of memory cells having string select gates, memory devices incorporating such strings, and methods of accessing and forming the same
First Claim
Patent Images
1. A string of memory cells, comprising:
- one or more first memory cells;
one or more second memory cells; and
a string select gate having a first channel structure and a second channel structure;
wherein the one or more first memory cells and the one or more second memory cells are serially-connected to collectively define the string of memory cells; and
wherein the string select gate is configured to concurrently selectively couple a first end of the string of memory cells to a data line through the first channel structure and a second end of the string of memory cells to a source line through the second channel structure.
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Abstract
Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.
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Citations
37 Claims
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1. A string of memory cells, comprising:
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one or more first memory cells; one or more second memory cells; and a string select gate having a first channel structure and a second channel structure; wherein the one or more first memory cells and the one or more second memory cells are serially-connected to collectively define the string of memory cells; and wherein the string select gate is configured to concurrently selectively couple a first end of the string of memory cells to a data line through the first channel structure and a second end of the string of memory cells to a source line through the second channel structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A memory device, comprising:
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a data line; a source line; a first stack of series coupled memory cells; a second stack of series coupled memory cells adjacent the first stack where a first end of the first stack is selectively coupled to a first end of the second stack; and a string select gate formed between a second end of the first stack and a second end of the second stack and having a first channel structure and a second channel structure, wherein the string select gate is configured to concurrently selectively couple the second end of the first stack to the data line through the first channel structure and the second end of the second stack to the source line through the second channel structure. - View Dependent Claims (14, 15)
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16. A memory device, comprising:
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a data line; a source line; a first string of series coupled memory cells formed along a first side of a first column and along a side of a second column, where the side of the second column is adjacent to the first side of the first column; a second string of series coupled memory cells formed along a second side of the first column and along a side of a third column, where the side of the third column is adjacent to the second side of the first column; a first string select gate formed between a top end of the first column and a top end of the second column and having a first channel structure between the first string select gate and the first column and a second channel structure between the first string select gate and the second column; and a second string select gate formed between a top end of the first column and a top end of the third column and having a first channel structure between the second string select gate and the first column and a second channel structure between the second string select gate and the third column; wherein the first string select gate is configured to couple the top end of the first column to the source line and to couple the top end of the second column to the data line when the first string select gate is activated; and wherein the second string select gate is configured to couple the top end of the first column to the source line and to couple the top end of the third column to the data line when the second string select gate is activated. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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23. A memory device, comprising:
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a data line; a first source line; a second source line; a first string of series coupled memory cells formed along a first side of a first column and along a side of a second column, where the side of the second column is adjacent to the first side of the first column; a second string of series coupled memory cells formed along a second side of the first column and along a side of a third column, where the side of the third column is adjacent to the second side of the first column; a first string select gate formed between a top end of the first column and a top end of the second column and having a first channel structure between the first string select gate and the first column and a second channel structure between the first string select gate and the second column; and a second string select gate formed between a top end of the first column and a top end of the third column and having a first channel structure between the second string select gate and the first column and a second channel structure between the second string select gate and the third column; wherein the first string select gate is configured to couple the top end of the first column to the data line and to couple the top end of the second column to the first source line when the first string select gate is activated; and wherein the second string select gate is configured to couple the top end of the first column to the data line and to couple the top end of the third column to the second source line when the second string select gate is activated. - View Dependent Claims (24)
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25. A memory device, comprising:
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a data line; a source line; a first column formed vertically on a semiconductor substrate, wherein the first column comprises a first string of serially-connected memory cells formed along a vertical wall of the first column; a second column formed vertically on the semiconductor substrate, wherein the second column comprises a second string of serially-connected memory cells formed along a vertical wall of the second column adjacent to the first string of serially-connected memory cells; and a string select gate, wherein the string select gate is formed between a top portion of the first column and a top portion of the second column and comprises a first channel structure between the string select gate and the first column and a second channel structure between the string select gate and the second column; wherein the string select gate is configured to couple a top memory cell of first string to the data line and a top memory cell of the second string to the source line when the string select gate is activated. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A method of operating a memory device, the method comprising:
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activating a string select gate to couple a first end of a string of serially-connected memory cells to a data line through a first channel structure of the string select gate and to couple a second end of the string of serially-connected memory cells to a source line through a second channel structure of the string select gate when one or more memory cells of the string is selected for a memory device operation; and deactivating the string select gate to decouple the first end of the string of serially-connected memory cells from the data line and to decouple the second end of the string of serially-connected memory cells from the source line when no memory cell of the string of serially-connected memory cells is selected for a memory device operation. - View Dependent Claims (36)
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37. A method of forming a string of serially-connected memory cells, the method comprising:
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forming a first column and a second column over a semiconductor substrate, wherein the first and the second column each comprise alternating structures of dielectric and conductive material, and where the first and the second column are separated by a particular distance; forming a continuous charge storage structure over the first and second columns and a region of the semiconductor substrate between the first and the second columns; forming a continuous channel structure over the continuous charge storage structure; and forming a string select gate structure between a top structure of the alternating structures of the first column and a top structure of the alternating structures of the second column, wherein the string select gate is formed to concurrently selectively provide conductivity to a portion of the continuous channel structure between the string select gate structure and the top structure of the alternating structures of the first column, and to a portion of the continuous channel structure between the string select gate structure and the top structure of the alternating structures of the second column.
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Specification