Method of providing an operating voltage in a memory device and a memory controller for the memory device

• US 8,441,856 B2
• Filed: 11/04/2011
• Issued: 05/14/2013
• Est. Priority Date: 11/11/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Moo Sung, Hahn, Wook Ghee
• Primary Examiner(s): Lam, David
• Application Number:
  US13/289,282
• Publication Number:
  US 20120120727A1
• Time in Patent Office: 557 Days
• Field of Search: 36518517-18519, 365/185.23
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage.

Claims

1. A method of providing an operating voltage in a memory device, the method comprising:

applying a read voltage to a selected word line of a NAND string;

applying a first pass voltage to at least one unselected word line among unselected word lines adjacent to the selected word line of the NAND string; and

applying a second pass voltage to at least one other unselected word lines of the NAND string,

wherein applying the first pass voltage comprises detecting the level of the read voltage and selecting the level of the first pass voltage according to the level of the read voltage,

wherein the level of the first pass voltage is higher than the level of the second pass voltage.

2. The method of claim 1, wherein applying the second pass voltage includes:

applying a the second pass voltage to at least one other unselected word lines among unselected word lines disposed on the bitline side of the selected wordline of in the NAND string; and

applying the second pass voltage to at least one of the other unselected word lines among unselected word lines disposed on the common source side of the selected wordline in the NAND string.

3. The method of claim 2, wherein the read voltage is a read voltage used in incremental step pulse programming (ISPP) or a read voltage used in a random access read operation.

4. A non-transient computer readable storage medium containing program codes configured for execution by a processor to carry out the method of claim 2.

5. The method of claim 1, wherein the selecting and applying the selected higher level of the first pass voltage comprises setting the voltage difference between the first pass voltage and the read voltage to a predetermined value.

6. The method of claim 1, the selecting and applying the first pass voltage comprises applying the first pass voltage at different levels according to whether the read voltage is a negative voltage or not a negative voltage.

7. A memory device comprising:

a memory cell array including a string of memory transistors connected to a plurality of word lines;

a voltage generator configured to provide an operating voltage for an operation in the memory cell array; and

a chip controller configured to control the voltage generator to apply a read voltage to a selected word line of the string, to apply a first pass voltage to at least one unselected word line among unselected word lines adjacent to the selected word line, and to apply a second pass voltage to other unselected word lines,

wherein the level of the first pass voltage is higher than the level of the second pass voltage,

wherein the chip controller controls the voltage generator to set the level of the first pass voltage based on the level of the read voltage.

8. The memory device of claim 7, wherein applying the second pass voltage to other unselected word lines includes

applying the second pass voltage to at least one other unselected word line among unselected word lines disposed on the bitline side of the selected wordline in the NAND string;

and

applying the second pass voltage to at least one of the other unselected word lines among unselected word lines disposed on the common source side of the selected wordline in the NAND string.

9. The memory device of claim 8, wherein the chip controller controls the voltage generator to set the level difference between the first pass voltage and the read voltage to a predetermined value.

10. The memory device of claim 8, wherein the read voltage is a verify read voltage used in incremental step pulse programming (ISPP) or a read voltage used in a random access read operation.

11. The memory device of claim 7, wherein the chip controller applies the first pass voltage at different levels according to whether the read voltage is a negative voltage or not a negative voltage.

12. A memory system comprising:

a memory device including an array of memory transistors connected to a plurality of word lines; and

a memory controller configured to control the memory device to apply a read voltage to a selected word line, apply a first pass voltage to at least one unselected word line among unselected word lines adjacent to the selected word line, and apply a second pass voltage to the other unselected word lines, other than the at least one unselected word line to which the first pass voltage is applied,

wherein the chip controller controls the voltage generator to set the level of the first pass voltage based on the level of the read voltage.

13. The memory system of claim 12, wherein the memory device further includes:

a voltage generator configured to provide an operating voltage for an operation in the memory transistor array based on control of the memory controller.

14. The memory system of claim 13, wherein the memory device further includes an interface circuit to interface with the memory controller.

15. The memory system of claim 13, wherein the memory system is implemented as a SSD (solid state drive) or a memory card.

16. The memory system of claim 13, wherein the operating voltage comprises a program operation voltage, a read operation voltage and a verify read operation voltage, and the first pass voltage and the second pass voltage.

17. The memory device of claim 12, wherein applying the second pass voltage to other unselected word lines includes:

applying a second pass voltage to at least one other unselected word line among unselected word lines disposed on the bitline side of the selected wordline in the NAND string; and

applying the second pass voltage to at least one of the other unselected word lines among unselected word lines disposed on the common source side of the selected wordline in the NAND string.

18. A method of reading data from a non-volatile memory device, the method comprising:

applying a read voltage to a selected word line of a NAND string in the memory device; and

detecting the level of the read voltage being applied to the selected word line and applying a first pass voltage to a first unselected word line adjacent to the selected word line, wherein the level of the first pass voltage depends upon the level of the read voltage, while applying a second pass voltage to another unselected word line of the NAND string, wherein the level of the first pass voltage is higher than the level of the second pass voltage.

19. The method of claim 18, wherein the level of the first pass voltage is higher than the detected level of the read voltage by a predetermined difference value.

20. The method of claim 18, further comprising applying the first pass voltage to a second unselected word line adjacent to the selected word line while applying the first pass voltage to the first unselected word line.

21. The method of claim 18, wherein the read voltage applied to the selected word line at a first time is a verify read voltage used in incremental step pulse programming (ISPP).

22. The method of claim 21, wherein the read voltage applied to the selected word line at a second time later than the first time is a read voltage used in a random access read operation.