Simultaneous data packet processing
First Claim
1. A packet controller for simultaneous processing of data packets transmitted via a plurality of communication channels, the packet controller comprising:
- a plurality of inputs to receive a respective plurality of data packet start signals from a plurality of transceivers, each of the plurality of data packet start signals being indicative of a start of reception of a data packet by a respective one of the plurality of transceivers on a respective one of the plurality of communication channels;
a clock source to supply a periodic clock signal;
a plurality of independent processing modules coupled to the respective plurality of inputs to simultaneously process the plurality of data packet start signals, wherein each of the plurality of independent processing modules implements a respective state machine driven by the periodic clock signal to process a respective data packet start signal independently of every other one of the plurality of processing modules;
an output to transmit an output signal indicative of a presence of at least one data packet on one or more of the plurality of communication channels; and
a mode selection input to receive a selection signal from a processor to select between at least a receive mode and a control mode of operation of the packet controller, wherein;
the receive mode corresponds to receiving data packets from the plurality of transceivers and forwarding the received data packets to the processor, andthe control mode corresponds to receiving control data from the processor and forwarding the received control data to a specified one of the plurality of transceivers.
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Accused Products
Abstract
A packet controller for simultaneous processing of data packets transmitted via a plurality of communication channels includes a plurality of inputs to receive a respective plurality of signals, such that each of the plurality of signals is indicative of a presence of a data packet on a respective one of the plurality of communication channels, a clock source to supply a periodic clock signal, a plurality of independent processing modules coupled to the respective plurality of inputs to simultaneously process the plurality of signals, such that each of the plurality of independent processing modules implements a respective state machine driven by the periodic clock signal to process the respective signal independently of every other one of the plurality of processing modules, and an output to transmit an output signal indicative of a presence of at least one data packet on one or more of the plurality of communication channels.
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Citations
17 Claims
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1. A packet controller for simultaneous processing of data packets transmitted via a plurality of communication channels, the packet controller comprising:
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a plurality of inputs to receive a respective plurality of data packet start signals from a plurality of transceivers, each of the plurality of data packet start signals being indicative of a start of reception of a data packet by a respective one of the plurality of transceivers on a respective one of the plurality of communication channels; a clock source to supply a periodic clock signal; a plurality of independent processing modules coupled to the respective plurality of inputs to simultaneously process the plurality of data packet start signals, wherein each of the plurality of independent processing modules implements a respective state machine driven by the periodic clock signal to process a respective data packet start signal independently of every other one of the plurality of processing modules; an output to transmit an output signal indicative of a presence of at least one data packet on one or more of the plurality of communication channels; and
a mode selection input to receive a selection signal from a processor to select between at least a receive mode and a control mode of operation of the packet controller, wherein;the receive mode corresponds to receiving data packets from the plurality of transceivers and forwarding the received data packets to the processor, and the control mode corresponds to receiving control data from the processor and forwarding the received control data to a specified one of the plurality of transceivers. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A packet controller for simultaneous processing of data packets transmitted via a plurality of communication channels, the packet controller comprising:
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a plurality of inputs to receive a respective plurality of data packet start signals from a plurality of transceivers, each of the plurality of data packet start signals being indicative of a start of reception of a data packet by a respective one of the plurality of transceivers on a respective one of the plurality of communication channels; a clock source to supply a periodic clock signal; a plurality of independent processing modules coupled to the respective plurality of inputs to simultaneously process the plurality of data packet start signals, wherein each of the plurality of independent processing modules implements a respective state machine driven by the periodic clock signal to process a respective data packet start signal independently of every other one of the plurality of processing modules; an output to transmit an output signal indicative of a presence of at least one data packet on one or more of the plurality of communication channels; a master serial parallel interface (SPI) coupled to exchange data with a processor, the master SPI including; a master output, slave input (MOSI) to receive transceiver control data from the processor; a master input, slave output (MISO) to transmit data packets to the processor; and a serial clock input (SCLK) to receive a master clock signal from the processor; and a plurality of slave SPIs coupled to the plurality of transceivers, each one of the plurality of SPIs including; a MISO to receive the data packets from a respective one of the plurality of transceivers; and a MOSI to forward the transceiver control data to the respective one of the plurality of transceivers; and a serial clock input (SCLK) to forward the master clock signal to the respective one of the plurality of transceivers.
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9. A method of processing data packets on a communication link having a plurality of wireless communication channels, the method comprising:
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simultaneously capturing a plurality of wireless signals, each associated with a respective one of the plurality of wireless communication channels, to generate a respective plurality of electronic signals, the respective plurality of electronic signals including; a plurality of data packet start signals received at a first plurality of inputs, each of the plurality of data packet start signals being indicative of a start of reception of a data packet by a respective one of a plurality of transceivers on a respective one of the wireless plurality of communication channels, and a plurality of data packet signals received at a second plurality of inputs, each of the plurality of data packet signals conveying the data packet received by the respective one of the plurality of transceivers on the respective one of the wireless plurality of communication channels; and processing the plurality of electronic signals in parallel, including; obtaining a periodic clock signal; simultaneously driving a plurality of state machines implemented by a plurality of independent processing modules by using the periodic clock signal to retrieve received data packets corresponding to the plurality of data packet start signals, wherein each of the plurality of state machines corresponds to the respective one of the plurality of wireless communication channels and uses a respective one of the plurality of electronic signals; multiplexing the retrieved data packets by using a multiplexer coupled to the plurality of independent processing modules; and generating, by an output coupled to the multiplexer, a data stream including the multiplexed, retrieved data packets for subsequent processing. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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Specification