High performance vertically emitting lasers

• US 8,442,084 B2
• Filed: 10/03/2002
• Issued: 05/14/2013
• Est. Priority Date: 10/03/2002
• Status: Active Grant

• Current Assignee: Laser Operations, LLC
• Original Assignee: Laser Operations, LLC
• Inventors: Ungar, Jeffrey E.
• Primary Examiner(s): Stultz, Jessica
• Assistant Examiner(s): FORDE, DELMA ROSA
• Application Number:
  US10/264,534
• Publication Number:
  US 20040066817A1
• Time in Patent Office: 3,876 Days
• Field of Search: 372 43- 501, 372/99, 372/102, 372/92, 372/96, 372/107, 257/777, 257/50.124
• US Class Current: 372/44.011
• CPC Class Codes: H01S 5/1085 Oblique facets
• CPC Class Codes: H01S 5/12 the resonator having a periodic structure, e.g. in distributed feedback [DFB] lasers comprising a photonic bandgap structure H01S5/11; surface-emitting lasers H01S5/18
• CPC Class Codes: H01S 5/125 Distributed Bragg reflector [DBR] lasers
• CPC Class Codes: H01S 5/18 Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
• CPC Class Codes: H01S 5/2201 in a specific crystallographic orientation
• CPC Class Codes: H01S 5/3202 grown on specifically orientated substrates, or using orientation dependent growth

Abstract

A semiconductor laser that has a reflective surface. The reflective surface redirects the light of an edge emitting laser diode to emit from the top or bottom surface of the diode. The laser may include a gain layer and a feedback layer located within a semiconductive die. The gain and feedback layers generate a laser beam that travels parallel to the surface of the die. The reflective surface reflects the laser beam 90 degrees so that the beam emits the die from the top or bottom surface. The reflective surface can be formed by etching a vicinally oriented III-V semiconductive die so that the reflective surface extends along a (111)A crystalline plane of the die.

Claims

1. A semiconductor laser, comprising:

a semiconductive die that has a top surface and includes a laser strip, said laser strip including;

a gain layer;

a diffraction grating feedback layer that together with said gain layer create a laser beam; and

,

a reflective surface located on a (111)A crystalline plane of said semiconductive die and located at a 45 degree angle relative to said top surface, said reflective surface reflects said laser beam to exit said top surface.

2. The semiconductor laser of claim 1, wherein said semiconductive die is fabricated from III-V compound semiconducting crystals.

3. The semiconductor laser of claim 1, wherein a top surface of said semiconductive die is located at an angle relative to a (100) crystalline plane of said semiconductive die.

4. The semiconductor laser of claim 1, wherein said semiconductive die includes an exit facet.

5. The semiconductor laser of claim 1, wherein said reflective surface is located along a groove that extends across a portion of a top surface of said semiconductive die.

6. A method for operating a semiconductor laser, comprising:

generating a laser beam in a laser strip located within a semiconductive die, the semiconductive die having a top surface; and

,

reflecting the laser beam from a reflective surface of a semiconductor die 90 degrees so that the laser beam exits the top surface of the semiconductor die, the reflective surface being located in the laser strip and on a (111)A crystalline plane of the semiconductive die at a 45 degree angle relative to the top surface.

7. A method for fabricating a semiconductor laser, comprising:

forming a mask on a top surface of a semiconductive wafer such that there is an unmasked portion of the semiconductive wafer;

etching the unmasked portion of the semiconductive wafer to create a reflective surface that extends on a (111)A crystalline plane of the semiconductive wafer and is located at a 45 degree angle relative to the top surface; and

,

cutting a semiconductive die from the semiconductive wafer.

8. The method of claim 7, wherein the semiconductive wafer is fabricated with III-V compound semiconducting crystals.

9. The method of claim 7, further comprising cutting the semiconductive wafer so that a top surface of the semiconductive wafer is located at an angle relative to a (100) crystalline plane of the semiconductive wafer.