Pulse signal output circuit and shift register
First Claim
1. A pulse signal output circuit comprising:
- a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor;
an eighth transistor;
a ninth transistor; and
a tenth transistor,wherein a first terminal of the first transistor, a first terminal of the second transistor, and a first output terminal are electrically connected to one another,wherein a first terminal of the third transistor, a first terminal of the fourth transistor, and a second output terminal are electrically connected to one another,wherein a first terminal of the fifth transistor, a first terminal of the sixth transistor, and a first terminal of the seventh transistor are electrically connected to one another,wherein a gate terminal of the first transistor, a gate terminal of the third transistor, and a second terminal of the seventh transistor are electrically connected to one another,wherein a gate terminal of the second transistor, a gate terminal of the fourth transistor, a gate terminal of the sixth transistor, a first terminal of the eighth transistor, and a first terminal of the ninth transistor are electrically connected to one another,wherein a second terminal of the eighth transistor and a first terminal of the tenth transistor are electrically connected to each other,wherein a ratio W/L of a channel width W to a channel length L of the first transistor and a ratio W/L of a channel width W to a channel length L of the third transistor are each larger than a ratio W/L of a channel width W to a channel length L of the sixth transistor,wherein a ratio W/L of a channel width W to a channel length L of the fifth transistor is larger than the ratio W/L of the channel width W to the channel length L of the sixth transistor,wherein the ratio W/L of the channel width W to the channel length L of the fifth transistor is equal to a ratio W/L of a channel width W to a channel length L of the seventh transistor, andwherein the ratio W/L of the channel width W to the channel length L of the third transistor is larger than a ratio W/L of a channel width W to a channel length L of the fourth transistor.
1 Assignment
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Accused Products
Abstract
An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
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Citations
10 Claims
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1. A pulse signal output circuit comprising:
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a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; an eighth transistor; a ninth transistor; and a tenth transistor, wherein a first terminal of the first transistor, a first terminal of the second transistor, and a first output terminal are electrically connected to one another, wherein a first terminal of the third transistor, a first terminal of the fourth transistor, and a second output terminal are electrically connected to one another, wherein a first terminal of the fifth transistor, a first terminal of the sixth transistor, and a first terminal of the seventh transistor are electrically connected to one another, wherein a gate terminal of the first transistor, a gate terminal of the third transistor, and a second terminal of the seventh transistor are electrically connected to one another, wherein a gate terminal of the second transistor, a gate terminal of the fourth transistor, a gate terminal of the sixth transistor, a first terminal of the eighth transistor, and a first terminal of the ninth transistor are electrically connected to one another, wherein a second terminal of the eighth transistor and a first terminal of the tenth transistor are electrically connected to each other, wherein a ratio W/L of a channel width W to a channel length L of the first transistor and a ratio W/L of a channel width W to a channel length L of the third transistor are each larger than a ratio W/L of a channel width W to a channel length L of the sixth transistor, wherein a ratio W/L of a channel width W to a channel length L of the fifth transistor is larger than the ratio W/L of the channel width W to the channel length L of the sixth transistor, wherein the ratio W/L of the channel width W to the channel length L of the fifth transistor is equal to a ratio W/L of a channel width W to a channel length L of the seventh transistor, and wherein the ratio W/L of the channel width W to the channel length L of the third transistor is larger than a ratio W/L of a channel width W to a channel length L of the fourth transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification