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Method and apparatus for protecting data using variable size page stripes in a FLASH-based storage system

  • US 8,443,136 B2
  • Filed: 12/17/2010
  • Issued: 05/14/2013
  • Est. Priority Date: 08/11/2009
  • Status: Active Grant
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First Claim
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1. A memory system comprising:

  • a plurality of FLASH memory chips, each of the plurality of FLASH memory chips having substantially the same physical construction and being associated with a plurality of physical memory locations, each having a physical memory address, the physical memory locations of each FLASH memory chip being grouped together to form blocks and planes, wherein a block reflects a group of FLASH memory locations that are erased at the same time and a plane reflects a group of blocks that utilize common circuitry for the performance of memory access operations;

    a system controller that includes an external communication bus interface for receiving WRITE requests from an external host device, wherein each WRITE request includes a data item and a logical memory address associated with the data item, the system controller further comprising a plurality of internal communication bus interfaces, each allowing the system controller to write data into physical memory locations associated with one or more of the FLASH memory chips; and

    a plurality of internal data communication buses, each internal data communications bus coupling one or more of the FLASH memory chips to an internal communication bus interface of the system controller;

    wherein the system controller is configured to associate each physical memory address with status data indicating whether the data stored at the physical memory address is invalid data;

    wherein the system controller is configured, for each WRITE request, to;

    (1) determine whether the logical memory address associated with the received data item was previously associated with a physical memory address;

    (2) if the logical memory address was previously associated with a physical memory address, change the status data for the previously associated physical memory address to indicate that the previously stored data is no longer valid;

    (3) identify an available physical memory location where the received data can be stored that is different from the previously associated physical memory address, the controller identifying the available physical memory location from at least one free blocks buffer, the at least one free blocks buffer containing one or more free blocks entries, each entry identifying a group of free blocks that have been defined by the controller as a free blocks group, each free blocks group having been previously erased and ready for storage of data, each block within a free blocks group storing one data item within a group of associated data items such that the number of blocks in a free blocks group equals the number of data items within a group of associated data items;

    (4) write the received data into the identified available physical memory address; and

    (5) update a table to associate the received logical memory address with the identified available physical memory address so as to translate the logical memory address provided by the external host to a physical memory address and to write the data item provided as part of the WRITE request to the physical memory location corresponding to the physical memory address;

    wherein the system controller is further configured to;

    (a) detect data errors that occur as a result of READ operations and maintain records of identified data errors and the plane associated with each data error;

    (b) designate a plane within a given FLASH memory chip as bad whenever the number of detected data errors associated with that plane exceeds a predetermined number; and

    wherein the system controller is further configured to;

    (i) associate a number of data items received through a plurality of WRITE requests with each other to form a group of received data items;

    (ii) generate data protection information for each group and write the data protection information to a physical memory location;

    (iii) perform the translation of the received logical memory addresses for the data items in the group and select the physical memory location for storage of the data protection information such that each of the data items is stored in a physical memory location within a FLASH memory chip that is different from the FLASH memory chips in which the other data items and the data protection information for the group of received data items are stored and such that each physical memory location of each data item within the group of data items is within a plane in the FLASH memory chip in which it is stored that physically corresponds to the planes in which the physical memory locations where the other data items in the group are stored; and

    (iv) dynamically select the number of data items used to form each group to not use any memory locations within the plane of the given FLASH memory chip that are designated as bad, such that the number of data items in one group of received data items differs from the number of data items in a second group of received data items such that the one group has a data item stored in physical memory locations within corresponding planes of each of the FLASH memory chips and such that the second group has a data item stored in corresponding planes of each of the FLASH memory chips except for the corresponding plane of the given FLASH memory chip which was designated as bad.

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