Throttling computational units according to performance sensitivity
First Claim
1. A method comprising:
- accessing performance data indicative of performance sensitivity of each of a plurality of computational units of a computer system to a change in performance capability;
determining a subset of one or more of the computational units among the plurality of the computational units that are least sensitive to change in performance capability based on the performance data; and
limiting performance of the subset of the plurality of computational units in the computer system.
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Abstract
A power allocation strategy limits performance of a subset of a plurality of computational units in a computer system according to performance sensitivity of each of the plurality of computational units to a change performance capability, e.g., frequency change. The performance of the subset of computational units may be limited by setting a power state in which the subset may be operated and/or reducing a current power state of the subset to a lower power state. The subset whose performance is limited includes computational units that are least performance sensitive according to stored sensitivity data. The subset may include one or more processing cores and performance of the one or more processing cores may be limited in response to a CPU-bounded application or graphics processing unit (GPU)-bounded application being executed.
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Citations
19 Claims
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1. A method comprising:
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accessing performance data indicative of performance sensitivity of each of a plurality of computational units of a computer system to a change in performance capability; determining a subset of one or more of the computational units among the plurality of the computational units that are least sensitive to change in performance capability based on the performance data; and limiting performance of the subset of the plurality of computational units in the computer system. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An apparatus comprising:
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a plurality of processing cores; a storage to store performance sensitivity information for the plurality of processing cores indicating performance sensitivity of each of the cores to a change in performance capability; and wherein the apparatus is configured to determine a subset of one or more of the processing cores among the plurality of the processing cores that are least sensitive to change in performance capability based on the performance data and to limit performance of the subset of the processing cores. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A non-transitory computer readable medium encoding a computer readable description of circuits that include,
a plurality of processing cores; -
a storage to store frequency sensitivity information for the plurality of processing cores indicating performance sensitivity of each of the cores to a change in frequency; and functional circuitry configured determine a subset of one or more of the processing cores among the plurality of the processing cores that are least sensitive to change in performance capability based on the performance data and to limit performance of each of the subset of the processing cores.
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Specification