Methods and systems with transaction-level lockstep

• US 8,443,230 B1
• Filed: 12/15/2010
• Issued: 05/14/2013
• Est. Priority Date: 12/15/2010
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: James-Roxby, Philip B., Wittig, Ralph D., Bridgford, Brendan K., McGee, Robert M., DeFelice, Richard
• Primary Examiner(s): DUNCAN, MARC M
• Application Number:
  US12/969,355
• Time in Patent Office: 881 Days
• Field of Search: 714/11, 714/12
• US Class Current: 714/11
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 11/1683 at instruction level

Abstract

Methods and systems for redundant operation of a first and second processor are provided. A set of instructions is executed in parallel on the first and second processors. In response to a first access transaction for a peripheral device being issued from execution of an instruction by the first processor, the first processor suspends operation. In response to the first access transaction being a write transaction, the write transaction is not issued to the peripheral device until the second processor executes the instruction and issues a second access transaction that is equal to the write transaction. In response to the first access transaction being a read transaction, the read transaction is not issued to the peripheral device until the second processor executes the instruction.

Claims

1. A method for redundant operation of a plurality of processors, the plurality of processors including at least a first processor and a second processor, the method comprising:

executing a same set of instructions in parallel on the first and second processors, each of the first and second processors coupled to a respective first and second status registers;

polling only the first status register for indication of a first transaction for a peripheral device being issued from execution of an instruction by the first processor; and

in response to the first status register indicating the first access transaction, performing steps including;

suspending operation of the first processor;

polling the second status register for indication of a second access transaction being issued from execution of the instruction by the second processor;

in response to the second status register indicating the second transaction and in response to the first access transaction being a write transaction, waiting to issue the write transaction to the peripheral device until the second processor executes the instruction and issues a second access transaction that is equal to the write transaction; and

in response to the second status register indicating the second transaction and in response to the first access transaction being a read transaction, waiting to issue the read transaction to the peripheral device until the second processor executes the instruction.

2. The method of claim 1, wherein the steps further include:

buffering the first access transaction in a first data register of a first buffer memory;

setting the first status register in the first buffer memory to a pending status, the setting of the first status register to the pending status causing the first processor to suspend operation;

polling the second status register in a second buffer memory until the second status register has the pending status; and

in response to a polled pending status from the second status register, performing steps including;

in response to the first access transaction being a read transaction, issuing the read transaction to the peripheral device; and

in response to the first access transaction being a write transaction and the first data register in the first buffer memory having contents equal to contents of a second data register in the second buffer memory, issuing the write transaction to the peripheral device.

3. The method of claim 2, wherein the steps further include:

in response to the first access transaction being a write transaction and the first data register having contents different from the second data register, setting the first and second status registers to an error status.

4. The method of claim 3, wherein the steps further include, in response to the first and second status registers having the error status, re-synchronizing the first and second processors for redundant operation.

5. The method of claim 2, wherein the steps further include:

in response to the instruction executed by the second processor issuing the second access transaction for the peripheral device;

buffering the second access transaction in the second data register in the second buffer memory; and

setting the second status register in the second buffer memory to the pending status, the setting of the second status register to the pending status causing the second processor to suspend operation.

6. The method of claim 5, wherein the steps further include, causing the first and second processors to resume operation by clearing the pending status of the first and second status registers of the respective first and second buffer memories.

7. The method of claim 5, wherein the first and second buffer memories each include a status register and a corresponding data register associated with each of a plurality of peripheral device addresses.

8. The method of claim 5, wherein the first and second processors are configured to buffer access transactions in the respective first and second buffer memories only when operating in a lock-step mode.

9. The method of claim 2, wherein:

the first buffer memory is included in a processor system portion of a system-on-chip (SOC) integrated circuit; and

the second buffer memory is located within a programmable logic region of the SOC integrated circuit.

10. A computing system, comprising:

a first processor and a second processor, the computing system configured to execute a same set of instructions in parallel on the first and second processors;

first and second buffer memories coupled to the first and second processors, respectively, and configured to buffer access transactions issued by the first processor and second processor for a plurality of peripheral device addresses, the first and second buffer memories including first and second status registers;

wherein the first processor is configured to suspend operation in response to execution of an instruction that issues a first access transaction to one of the peripheral device addresses;

a controller circuit coupled to the first and second buffer memories and configured to;

poll only the first status register for indication of a first transaction for a peripheral device being issued from execution of an instruction by the first processor;

in response to the first status register indicating the first access transaction, performing steps including;

polling the second status register for indication of a second access transaction being issued from execution of the instruction by the second processor;

in response to the second status register indicating the second transaction and in response to the first access transaction being a write transaction, wait to issue the write transaction to the one of the peripheral device addresses until the second processor executes the instruction and issues a second access transaction that is equal to the write transaction; and

in response to the second status register indicating the second transaction and in response to the first access transaction being a read transaction, wait to issue the read transaction to the one of the peripheral device addresses until the second processor executes the instruction.

11. The computing system of claim 10, wherein:

each buffer memory includes a data register and a corresponding status register associated with each of the plurality of peripheral device addresses, respectively;

the first processor is further configured to;

set the status register associated with the one of the peripheral device addresses to a pending status in response to buffering an access transaction in the corresponding data register in the first buffer memory; and

suspend operation in response to the pending status in the status register in the first buffer memory and associated with the one of the peripheral device addresses;

the second processor is configured to;

set the status register associated with the one of the peripheral device addresses to a pending status in response to buffering an access transaction in the corresponding data register in the second buffer memory; and

suspend operation in response to the pending status in the status register in the second buffer memory and associated with the one of the peripheral device addresses; and

the controller circuit is further configured to;

in response to the first access transaction issued by the first processor, poll the status register of the second buffer memory and corresponding to the one of the peripheral device addresses; and

in response to a polled pending status in the status register of the second buffer memory and corresponding to the one of the peripheral device addresses, perform operations including;

in response to the first access transaction being a read transaction, issuing the read transaction to the one of the peripheral device addresses;

in response to the first access transaction being a write transaction and the data registers in the first and second buffer memories and associated with the one of the peripheral device addresses being equal, issuing the write transaction to the one of the peripheral device addresses; and

in response to the first access transaction completing, clearing the pending status of the status registers associated with the one of the peripheral device addresses.

12. The computing system of claim 11, wherein the controller circuit is further configured to, in response to the access transaction being a write transaction and the data registers associated with the one of the peripheral device addresses not being equal, set the status registers associated with the one of the peripheral device addresses in the first and second buffer memories to an error status.

13. The computing system of claim 12, wherein the computing system is further configured to, in response to the status registers of the first and second buffer memories and associated with the one of the peripheral device addresses having a value indicating an error, synchronize the first and second processors for lock-step operation.

14. The computing system of claim 11, wherein the first and second processors are further configured to resume operation in response to a cleared pending status in the status registers of the first and second buffer memories and associated with the one of the peripheral device addresses.

15. A programmable integrated circuit (IC), comprising:

programmable logic resources;

routing resources coupled to the programmable logic resources;

a plurality of processors including at least a first processor and a second processor, the first and second processors configured to execute a same set of instructions in parallel;

first and second buffer memories coupled to the first and second processors, respectively, and configured to buffer access transactions issued by the first and second processors for a plurality of peripheral device addresses, the first and second buffer memories including first and second status registers;

wherein the first processor is configured to suspend operation in response to execution of an instruction that issues a first access transaction to one of the peripheral device addresses; and

a controller circuit coupled to the first and second buffer memories and configured to;

poll only the first status register for indication of a first transaction for a peripheral device being issued from execution of an instruction by the first processor;

in response to the first status register indicating the first access transaction, performing steps including;

polling the second status register for indication of a second access transaction being issued from execution of the instruction by the second processor;

in response to the second status register indicating the second transaction and in response to the first access transaction being a write transaction, wait to issue the write transaction until the second processor executes the instruction and issues a second access transaction that is equal to the write transaction; and

in response to the second status register indicating the second transaction and in response to the first access transaction being a read transaction, wait to issue the read transaction until the second processor executes the instruction.

16. The programmable IC of claim 15, wherein:

the first and second buffer memories further include a data register and a corresponding status register associated with each of the plurality of peripheral device addresses, respectively; and

the controller circuit is further configured to;

in response to the first access transaction issued by the first processor for the one of the peripheral device addresses, poll the status register of the second buffer memory and associated with the one of the peripheral device addresses; and

in response to a polled pending status, perform steps including;

in response to the first access transaction being a read transaction, issuing the read transaction to the one of the peripheral device addresses;

in response to the first access transaction being a write transaction and the data registers in the first and second buffer memories and associated with the one of the peripheral device addresses being equal, issuing the write transaction to the one of the peripheral device addresses; and

in response to the first access transaction completing, clear the pending status of the status registers associated with the one of the peripheral device addresses.

17. The programmable IC of claim 16, wherein the first processor is further configured to, in response to execution of the instruction that issues the first access transaction, set the status register associated with the one of the peripheral device addresses to a pending status.

18. The programmable IC of claim 17, wherein the control circuit is further configured to, in response to the first access transaction being a write transaction and the data registers associated with the one of the peripheral device addresses not being equal, set the status registers associated with the one of the peripheral device addresses to an error status.

19. The programmable IC of claim 17, wherein the first processor is further configured to resume operation in response to the cleared pending status in the status register associated with the one of the peripheral device addresses.

20. The programmable IC of claim 17, wherein the first and second processors are implemented in a system-on-chip embedded on the programmable IC.