Apparatus, system, and method for using multi-level cell solid-state storage as single level cell solid-state storage

• US 8,443,259 B2
• Filed: 06/22/2012
• Issued: 05/14/2013
• Est. Priority Date: 03/13/2009
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Fusion-IO Incorporated (Western Digital Corporation)
• Inventors: Thatcher, Jonathan, Flynn, David, Barnes, Ethan, Strasser, John, Wood, Robert, Zappe, Michael
• Primary Examiner(s): Ton, David
• Application Number:
  US13/531,240
• Publication Number:
  US 20120266046A1
• Time in Patent Office: 326 Days
• Field of Search: 365/185.24, 714/782, 714/763, 714/789, 714/819, 707/705, 711/103
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

An apparatus, system, and method are disclosed for storing information in a storage device that includes multi-level memory cells. The method involves storing data that is written to the storage device in the LSBs of the multi-level memory cells, and storing audit data in the MSBs of the multi-level memory cells. The audit data can be read separately from the data and used to determine whether or not there has been any unintended drift between states in the multi-level cells. The audit data may be used to correct data when the errors in the data are too numerous to be corrected using error correction code (ECC). The audit data may also be used to monitor the general health of the storage device. The monitoring process may run as a background process on the storage device. The storage device may transition the multi-level memory cells to operate as single-level memory cells.

Claims

1. A method comprising:

receiving a write command from a client;

setting a physical address for storing data associated with the write command to a physical address for one or more lower pages of one or more page pairs of a storage device, wherein each page pair comprises a lower page associated with a least significant bit (LSB) of a plurality of multi-level cells in the storage device; and

writing data associated with the write command received from the client to only the lower page in each page pair of the one or more page pairs.

2. The method of claim 1, further comprising validating data in the one or more lower pages using audit data from one or more upper pages associated with a most significant bit (MSB) of the multi-level cells.

3. The method of claim 1, further comprising storing audit data for the one or more lower pages in one or more upper pages of the one or more page pairs, the one or more upper pages associated with a most significant bit (MSB) of the multi-level cells.

4. The method of claim 3, further comprising searching for bit errors in the data stored in the one or more lower pages in response to determining that a number of detected bit errors in an error correcting code (ECC) chunk for the one or more lower pages exceeds a correctable bit error count.

5. The method of claim 4, wherein searching for bit errors in the data stored in the one or more lower pages further comprises searching the audit data in one or more upper pages paired to the one or more lower pages and determining that the one or more lower pages comprise suspect data bits in response to corresponding bits in the one or more upper pages not matching an expected value.

6. The method of claim 5, further comprising flipping one or more bits in the one or more lower pages corresponding to bits in the one or more upper pages that do not match the expected value.

7. The method of claim 1, wherein one or more hardware controllers that program the multi-level cells employ a two-phase programming model for page pairs.

8. The method of claim 7, further comprising increasing a guard band between two data states in the multi-level cells of the storage device by executing a first program phase to put the cell in an intermediate state, followed by a second program phase to put the cell in a final state.

9. The method of claim 1, further comprising setting the physical address for storing data to one or more upper pages of the one or more page pairs, in response to determining that reliability of storing data in the one or more lower pages has decreased below a threshold.

10. A system comprising:

a solid-state storage media comprising a plurality of multi-level cells;

a driver configured to receive a write command from a client, the write command comprising a logical block address;

a mapping logic module configured to map the logical block address received from the client to one or more page pairs, wherein each page pair comprises a lower page associated with a least significant bit (LSB) of the plurality of multi-level cells and an upper page associated with a most significant bit (MSB) of the multi-level cells; and

a hardware controller configured to write data associated with the write command to the lower page in each page pair of the one or more page pairs.

11. The system of claim 10, wherein the multi-level cells store n bits per cell by way of 2ⁿ progressively increasing voltage states, and wherein n bits of the multi-level cells are organized into page tuples in which each bit of the multi-level cells is addressable in a distinct page of the page tuple.

12. The system of claim 11, wherein n equals 2 and the page tuple comprises a page pair in which the lower page of the page pair corresponds to voltage states that are less than the maximum voltage state for the multi-level cells.

13. The system of claim 12, wherein the multi-level cells support four progressively increasing voltage states, and wherein the lower page corresponds to the first and third voltage states.

14. An apparatus comprising:

means for setting a physical address for storing data associated with the write command to a physical address for one or more lower pages of one or more page pairs of a storage device, wherein each page pair comprises a lower page associated with a least significant bit (LSB) of a plurality of multi-level cells in the storage device, and an upper page associated with a most significant bit (MSB) of the multi-level cells; and

means for writing data associated with the write command received from the client to the lower page in each page pair of the one or more page pairs, wherein audit data for the lower page in each page pair is stored in the upper page of each page pair.

15. The apparatus of claim 14, further comprising means for storing the audit data for the one or more lower pages in one or more upper pages of the one or more page pairs.

16. The apparatus of claim 15, further comprising means for searching for bit errors in the data stored in the one or more lower pages in response to determining that a number of detected bit errors in an error correcting code (ECC) chunk for the one or more lower pages exceeds a correctable bit error count.

17. The apparatus of claim 16, wherein the means for searching for bit errors in the data stored in the one or more lower pages further comprises means for searching the audit data in the one or more upper pages and determining that the one or more lower pages comprise suspect data bits in response to corresponding bits in the one or more upper pages not matching an expected value.

18. An apparatus comprising:

a mapping logic module configured to map a logical block address to a plurality of least significant bits (LSBs) and a plurality of most significant bits (MSBs) of a plurality of multi-level cells, the logical block address received from a client in a write command; and

a hardware controller configured to write data associated with the write command received from the client to the plurality of LSBs.

19. The apparatus of claim 18, wherein the hardware controller is configured to write the data associated with the write command only to the plurality of LSBs and to store audit data for the plurality of LSBs in the plurality of MSBs.

20. The apparatus of claim 18, wherein the plurality of LSBs are associated with one or more lower pages of one or more page pairs and the plurality of MSBs are associated with one or more upper pages of the one or more page pairs, the hardware controller writing the data only to the one or more lower pages of the one or more page pairs.

21. A computer program product comprising a non-transitory computer readable storage medium storing computer usable program code executable to perform operations comprising:

receiving a write command from a client, the write command comprising a logical block address;

mapping the logical block address received from the client to a plurality of least significant bits (LSBs) and a plurality of most significant bits (MSBs) of a plurality of multi-level cells; and

writing data associated with the write command received from the client to only the plurality of LSBs.

22. The computer program product of claim 21, further comprising storing audit data for the plurality of LSBs in the plurality of MSBs of the plurality of multi-level cells.

23. The computer program product of claim 21, wherein mapping the logical block address to the plurality of LSBs and the plurality of MSBs comprises mapping the logical block address to one or more page pairs of the storage device, wherein each page pairs comprises a lower page associated with the plurality of LSBs and an upper page associated with the plurality of MSBs.

24. The computer program product of claim 21, further comprising searching for bit errors in the data stored in the plurality of LSBs in response to determining that a number of detected bit errors in an error correcting code (ECC) chunk for the plurality of LSBs exceeds a correctable bit error count.

25. The computer program product of claim 24, wherein searching for bit errors in the data stored in the plurality of LSBs comprises searching audit data in the plurality of MSBs and determining that the plurality of LSBs comprise suspect data bits in response to corresponding bits in the plurality of MSBs not matching an expected value.