System and method for handling forward error correction code blocks in a receiver
First Claim
1. A method of handling forward error correction (FEC) code blocks in a receiver apparatus, comprising:
- detecting a plurality of binary code portions at predetermined positions in a number of successive signal frames containing a plurality of FEC code blocks;
comparing the binary code portions against a plurality of distributions of known patterns, wherein each of the distributions of known patterns represents a different distribution of scrambled synchronization bytes of a transport stream; and
generating a synchronization signal locked to a distribution of the FEC code blocks that is associated with one matched distribution of the known patterns into which most of the binary code portions map.
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Accused Products
Abstract
A receiver apparatus can identify a plurality of patterns corresponding to scrambled synchronization bytes of a transport stream in a number of successive signal frames containing FEC code blocks, determine a pattern distribution into which most of the patterns identified in the successive signal frames map, and generate a synchronization signal locked to a distribution of the FEC code blocks associated with the pattern distribution. With this synchronization signal, FEC code blocks can be timely handled in a reliable manner through a FEC decoder, making the receiver apparatus more efficient and robust. In other embodiments, methods of handling FEC code blocks in a receiver apparatus are also described.
2 Citations
20 Claims
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1. A method of handling forward error correction (FEC) code blocks in a receiver apparatus, comprising:
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detecting a plurality of binary code portions at predetermined positions in a number of successive signal frames containing a plurality of FEC code blocks; comparing the binary code portions against a plurality of distributions of known patterns, wherein each of the distributions of known patterns represents a different distribution of scrambled synchronization bytes of a transport stream; and generating a synchronization signal locked to a distribution of the FEC code blocks that is associated with one matched distribution of the known patterns into which most of the binary code portions map. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of handling forward error correction (FEC) code blocks in a receiver apparatus, comprising:
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identifying a plurality of patterns corresponding to scrambled synchronization bytes of a transport stream in a number of successive signal frames containing FEC code blocks; determining a pattern distribution into which most of the patterns identified in the successive signal frames map; and generating a synchronization signal locked to a distribution of the FEC code blocks associated with the pattern distribution. - View Dependent Claims (12)
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13. A receiver apparatus comprising:
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a symbol de-mapping unit adapted to de-map a plurality of data symbols and output a plurality of signal frames containing forward error correction (FEC) code blocks; a FEC code block synchronizer adapted to identify a plurality of patterns corresponding to scrambled synchronization bytes of a transport stream in a number of successive signal frames; determine a pattern distribution into which most of the patterns identified in the successive signal frames map; and generate a synchronization signal locked to a distribution of the FEC code blocks associated with the pattern distribution; and a FEC decoder adapted to process the FEC code blocks in accordance with the synchronization signal. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification