Method and apparatus for generating graphical representations of slack potential for slack paths

• US 8,443,334 B1
• Filed: 02/15/2012
• Issued: 05/14/2013
• Est. Priority Date: 01/14/2009
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Guzy, Przemek
• Primary Examiner(s): LEVIN, NAUM B
• Application Number:
  US13/396,662
• Time in Patent Office: 454 Days
• Field of Search: 716/113, 716/116, 716/122, 716/134, 716/139
• US Class Current: 716/139
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method for designing a system to be implemented on a target device includes computing slack potential of paths between components on the target device after timing analysis. A graphical representation of the slack potential and slack for the paths is generated. The graphical representation identifies that a design change is required for a first portion of the system associated with a first path and that a change in placement is required for a second portion of the system associated with the second path.

Claims

1. A method for managing data for a system to be implemented on a target device, the method comprising:

computing slack potential of paths between components on the target device after timing analysis; and

generating a graphical representation of the slack potential and slack for the paths, wherein the graphical representation identifies whether a design change is required for a first portion of the system associated with a first path and whether a change in placement is required for a second portion of the system associated with a second path, wherein at least one of the computing and generating procedures is performed by a processor.

2. The method of claim 1, wherein the slack potential of paths comprises a difference between actual slacks computed from timing analysis and slack values where routing delay is at a near optimum value.

3. The method of claim 2, wherein the near optimum value is determined from a fixed value used for all paths that is a smallest possible routing delay available.

4. The method of claim 2, wherein the near optimum value is determined based upon a type of connection used for a path.

5. The method of claim 2, wherein the near optimum value is determined using a heuristic algorithm that takes into account a number of fan-outs on a path, routing delay previously computed for the path, and system utilization.

6. The method of claim 1, wherein the paths are identified by a user and are associated with one or more of a source and destination.

7. The method of claim 1, wherein the paths are paths identified to not satisfying timing requirement from timing analysis.

8. The method of claim 1 further comprising performing timing analysis on the system that has been synthesized, placed, and routed on the target device.

9. The method of claim 8 further comprising:

receiving the design change to the first portion of the system and the change in placement to the second portion of the system from a designer; and

modifying one or more of synthesis, placement, and routing of the system on the target device in response to the design change and the change in placement.

10. A non-transitory computer readable medium including sequences of instructions stored thereon for causing a computer to execute a method comprising:

computing slack potential of paths between components of a system on a target device after timing analysis; and

generating a graphical representation of the slack potential and slack for the paths, wherein the graphical representation identifies whether a design change is required for a first portion of the system associated with a first path and whether a change in placement is required for a second portion of the system associated with a second path.

11. The non-transitory computer readable medium of claim 10, wherein the slack potential comprises a difference between actual slacks computed from timing analysis and slack values where routing delay is at a near optimum value.

12. The non-transitory computer readable medium of claim 11, wherein the near optimum value is determined from a fixed value used for all paths that is a smallest possible routing delay available.

13. The non-transitory computer readable medium of claim 11, wherein the near optimum value is determined based upon a type of connection used for a path.

14. The non-transitory computer readable medium of claim 11, wherein the near optimum value is determined using a heuristic algorithm that takes into account a number of fan-outs on the path, routing delay previously computed for a path, and system utilization.

15. The non-transitory computer readable medium of claim 10, wherein the paths are identified by a user and are associated with one or more of a source and destination.

16. The non-transitory computer readable medium of claim 10, wherein the paths are identified from paths not satisfy timing requirement from timing analysis.

17. The non-transitory computer readable medium of claim 10 further comprising performing timing analysis on the system that has been synthesized, placed, and routed on the target device.

18. The non-transitory computer readable medium of claim 17 further comprising:

receiving the design change to the first portion of the system and the change in placement to the second portion of the system from a designer; and

modifying one or more of synthesis, placement, and routing of the system on the target device in response to the design change and the change in placement.

19. A system designer comprising:

a timing analysis unit operable to compute slack for paths between components of a system on a target device; and

a slack potential analysis unit operable to compute slack potential for the paths and to generate a graphical representation of the slack potential and the slack for the paths, wherein the graphical representation identifies whether a design change is required for a first portion of the system associated with a first path and whether a change in placement is required for a second portion of the system associated with a second path.

20. The system designer of claim 19, wherein the paths are identified by a user.