Method and apparatus for manufacturing a multi layer chip capacitor

• US 8,443,498 B2
• Filed: 04/04/2011
• Issued: 05/21/2013
• Est. Priority Date: 06/21/2005
• Status: Expired due to Fees

• Current Assignee: Sehyang Industrial Co., Ltd.
• Original Assignee: Sehyang Industrial Co., Ltd.
• Inventors: Ha, Jae-Ho
• Primary Examiner(s): TRINH, MINH N
• Application Number:
  US13/079,573
• Publication Number:
  US 20110181999A1
• Time in Patent Office: 778 Days
• Field of Search: 29 2541- 2542, 361/311, 361/321.2, 257/758, 257/532, 438622-624
• US Class Current: 29/25.42
• CPC Class Codes: H01G 13/00 Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00
• CPC Class Codes: H01G 4/008 Selection of materials
• CPC Class Codes: H01G 4/012 Form of non-self-supporting electrodes
• CPC Class Codes: H01G 4/06 Solid dielectrics
• CPC Class Codes: H01G 4/085 Vapour deposited
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H01G 4/306 made by thin film techniques
• CPC Class Codes: Y10T 29/43 Electric condenser making
• CPC Class Codes: Y10T 29/435 Solid dielectric type
• CPC Class Codes: Y10T 29/49144 by metal fusion
• CPC Class Codes: Y10T 29/5313 Means to assemble electrical device
• CPC Class Codes: Y10T 29/53174 Means to fasten electrical component to wiring board, base, or substrate
• CPC Class Codes: Y10T 29/53178 Chip component

Abstract

The present invention carries out the vacuum deposition by setting a deposition angle between a single mask set including a shadow mask having a plurality of slits and a deposition source to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once, or adjusts slit patterns by relatively moving upper and lower mask sets that respectively include shadow masks having a plurality of slits and face each other to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once.

Claims

1. A method of manufacturing a multi-layer chip capacitor by depositing a dielectric layer and a conductor layer in the form of multi-layer chip, while a width of the conductor layer is narrower than a width of the dielectric layer, comprising:

positioning a dielectric layer deposition source to be perpendicular to a single shadow mask having a plurality of slits and a conductor layer deposition source to be oblique to the single shadow mask;

forming the dielectric layer and the conductor layer by evaporating evaporated particles from the respective deposition sources to pass through the slits and to be deposited on a substrate; and

moving a mask set, in which the shadow mask is mounted, in a height direction based on layer growth rates of the conductor layer and the dielectric layer during deposition of the conductor layer and the dielectric layer.

2. The method of manufacturing a multi-layer chip capacitor according to claim 1, wherein a range of a deposition angle for obliquely positioning the conductor layer deposition source is from 5 degrees to 45 degrees in the direction perpendicular to the shadow mask.

3. The method of manufacturing a multi-layer chip capacitor according to claim 1, further comprising repeating a control of the shadow mask to be separated from the substrate during the deposition of the conductor layer and the dielectric layer and of precisely adjusting the position of the separated shadow mask upwardly based on growth rates of the deposited layers every predetermined time period.

4. The method of manufacturing a multi-layer chip capacitor according to claim 1, further comprising controlling a mask set to move in the height direction to prevent a deposition layer formed on the substrate from being damaged by the shadow mask after the formation of the deposition layer and to be spaced apart from the substrate, and to be positioned in the horizontal direction defined as the width direct on and the longitudinal direction.

5. The method of manufacturing a multi-layer chip capacitor according to claim 1, further comprising using a shadow mask wherein a width directional cross-section of the slits of the shadow mask is a parallelogram and a longitudinal cross-section thereof is a trapezoid.

6. The method of manufacturing a multi-layer chip capacitor according to claim 1, further comprising using a shadow mask wherein a cross-section of the slits of the shadow mask is one of a parallelogram, a parallelogram with a step, a trapezoid, and a trapezoid with a step.

7. The method of manufacturing a multi-layer chip capacitor according to claim 1, further comprising depositing the dielectric layer and the conductor layer on a releasing layer formed on the substrate.

8. The method of manufacturing a multi-layer chip capacitor according to claim 1, further comprising placing the mask parallel to a planar surface of the substrate.

9. A method of manufacturing a multi-layer chip capacitor by depositing a dielectric layer and a conductor layer in the form of multi-layer chip, while a width of the conductor layer is narrower than a width of the dielectric layer, comprising:

positioning a dielectric layer deposition source to be perpendicular to a single shadow mask having a plurality of slits and a conductor layer deposition source to be oblique to the single shadow mask;

forming the dielectric layer and the conductor layer by evaporating evaporated particles from the respective deposition sources to pass through the slits and to be deposited on a substrate; and

repeating a control of the shadow mask to be separated from the substrate during deposition of the conductor layer and the dielectric layer and of precisely adjusting a position of the separated shadow mask upwardly based on growth rates of the deposited layers every predetermined time period.

10. A method of manufacturing a multi-layer chip capacitor by depositing a dielectric layer and a conductor layer in the form of multi-layer chip, while a width of the conductor layer is narrower than a width of the dielectric layer, comprising:

positioning a dielectric layer deposition source to be perpendicular to a single shadow mask having a plurality of slits and a conductor layer deposition source to be oblique to the single shadow mask;

forming the dielectric layer and the conductor layer by evaporating evaporated particles from the respective deposition sources to pass through the slits and to be deposited on a substrate; and

controlling a mask set to move in a height direction to prevent a deposition layer formed on the substrate from being damaged by the shadow mask after the formation of the deposition layer and to be spaced apart from the substrate, and to be positioned in a horizontal direction defined as a width direction and a longitudinal direction.