Package-in-package using through-hole via die on saw streets

• US 8,445,325 B2
• Filed: 06/26/2007
• Issued: 05/21/2013
• Est. Priority Date: 05/04/2007
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Do, Byung Tai, Kuan, Heap Hoe, Chow, Seng Guan
• Primary Examiner(s): Im, Junghwa M
• Application Number:
  US11/768,825
• Publication Number:
  US 20080272504A1
• Time in Patent Office: 2,156 Days
• Field of Search: 438/629, 438/637, 438/639, 438/113, 438/458, 438/462, 438/464, 257/797, 257/690
• US Class Current: 438/113
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68336 involving stretching of the auxiliary support post dicing
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13138 the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/14131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 : the item being metallic
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45139 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48145 : the bodies being stacked
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 : the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 : Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

Claims

1. A method of making a semiconductor device, comprising:

providing a first semiconductor die having top, bottom, and peripheral side surfaces;

providing a bond pad formed over the top surface;

providing an organic material disposed around the peripheral side surface and extending from the top surface to the bottom surface of the first semiconductor die;

after providing the organic material, forming a via through the organic material from the top surface to the bottom surface of the first semiconductor die;

after forming the via, providing a conductive material deposited in the via to form a conductive through hole via (THV) extending from the top surface to the bottom surface of the first semiconductor die;

providing a metal trace electrically connecting the conductive THV to the bond pad;

providing a redistribution layer (RDL) having an interconnection pad disposed over the top surface of the first semiconductor die;

mounting a second semiconductor die to the first semiconductor die; and

depositing an encapsulant over the first and second semiconductor die to form a package-in-package (PiP) semiconductor device.

2. The method of claim 1, further including electrically connecting the second semiconductor die to the first semiconductor die using a bond wire.

3. The method of claim 2, further including providing an underfill material disposed between the first and second semiconductor die.

4. The method of claim 3, further including providing a third semiconductor die attached to the second semiconductor die and wire-bonded to the conductive material.

5. A method of making a semiconductor device, comprising:

providing a first semiconductor die incorporating an organic material formed around a peripheral region of the first semiconductor die that extends from a top surface to a bottom surface of the first semiconductor die and a conductive through-hole via (THV) formed through the organic material, the first semiconductor die disposed over a substrate;

providing a second semiconductor die electrically connected to the conductive THV of the first semiconductor die; and

providing an encapsulant formed over the first and second semiconductor die to form a package-in-package (PiP) semiconductor device.

6. The method of claim 5, wherein the second semiconductor die is a wire-bond die, which is wire-bonded to the conductive THV.

7. The method of claim 5, wherein the second semiconductor die is wire-bonded to a bond pad which is coupled to the conductive THV.

8. The method of claim 5, further including providing a redistribution layer (RDL) incorporating an interconnection pad formed over the top surface of the first semiconductor die, wherein the first and second semiconductor die are electrically connected through a bump coupled to the interconnection pad.

9. The method of claim 5, further including providing an underfill material disposed between the first and second semiconductor die.

10. The method of claim 5, further including providing a third semiconductor die, coupled to the second semiconductor die, and wire-bonded to the conductive THV.

11. The method of claim 5, wherein the second semiconductor die is integrated into a leadframe package mounted to the first semiconductor die.

12. The method of claim 5, wherein the second semiconductor die is integrated into an array package mounted to the first semiconductor die.

13. The method of claim 5, wherein the second semiconductor die is integrated into an inverted top package mounted to the first semiconductor die.

14. The method of claim 13, further including mounting a third semiconductor die to the inverted top package.

15. The method of claim 5, wherein the second semiconductor die is integrated into an inverted bottom package disposed between the first semiconductor die and the substrate.

16. The method of claim 15, further including providing a third semiconductor die incorporating a conductive THV disposed along a peripheral surface of the third semiconductor die, wherein the third semiconductor die is disposed adjacent to the first semiconductor die.

17. The method of claim 16, further including providing an integrated passive device coupled to the conductive THV.

18. The method of claim 5, further including:

providing a bond pad formed over the top surface;

providing a metal trace electrically connecting the conductive THV to the bond pad; and

providing a redistribution layer (RDL) including an interconnection pad disposed over the top surface of the first semiconductor die.

19. The method of claim 18, further including electrically connecting the second semiconductor die to the first semiconductor die using a bump.

20. The method of claim 19, further including providing an underfill material disposed between the first semiconductor die and the second semiconductor die.

21. The method of claim 20, further including providing a third semiconductor die attached to the second semiconductor die and wire-bonded to the conductive material.

22. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

forming a bond pad over a first surface of the first semiconductor die;

forming an organic material around a peripheral region of the first semiconductor die and extending from the first surface to a second surface of the first semiconductor die opposite the first surface;

forming a via through the organic material from the first surface to the second surface of the first semiconductor die;

forming a conductive material in the via to provide a conductive through hole via (THV) extending from the first surface to the second surface of the first semiconductor die;

forming a conductive trace over the first surface of the first semiconductor die electrically connected between the conductive THV and the bond pad;

mounting a second semiconductor die to the first semiconductor die; and

depositing a first encapsulant over the first and second semiconductor die to form a package-in-package (PiP) semiconductor device.

23. The method of claim 22, further including forming a redistribution layer over the first surface of the first semiconductor die.

24. The method of claim 22, further including electrically connecting the second semiconductor die to the first semiconductor die using a bond wire.

25. The method of claim 22, further including depositing an underfill material between the first semiconductor die and the second semiconductor die.

26. The method of claim 22, further including:

mounting a third semiconductor die to the second semiconductor die; and

electrically connecting the third semiconductor die to the first semiconductor die.

27. The method of claim 26, wherein the third semiconductor die overhangs the second semiconductor die.

28. The method of claim 26, further including depositing a second encapsulant over the third semiconductor die prior to depositing the first encapsulant.

29. The method of claim 22, further including:

mounting a third semiconductor die to the first semiconductor die; and

electrically connecting the third semiconductor die to the first semiconductor die.

30. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

forming an organic material around a peripheral region of the first semiconductor die, the organic material extending from a first surface of the first semiconductor die to a second surface of the first semiconductor die opposite the first surface;

forming a conductive via through the organic material;

mounting a second semiconductor die to the first semiconductor die; and

depositing a first encapsulant over the first and second semiconductor die to form a package-in-package (PiP) semiconductor device.

31. The method of claim 30, further including:

forming a bond pad over the first surface of the first semiconductor die; and

forming a conductive trace over the first surface of the first semiconductor die electrically connected between the conductive via and the bond pad.

32. The method of claim 30, further including forming a redistribution layer over the first surface of the first semiconductor die.

33. The method of claim 30, further including electrically connecting the second semiconductor die to the first semiconductor die using a bump.

34. The method of claim 30, further including depositing an underfill material between the first semiconductor die and the second semiconductor die.

35. The method of claim 30, further including:

mounting a third semiconductor die to the second semiconductor die; and

electrically connecting the third semiconductor die to the second semiconductor die.

36. The method of claim 35, wherein the third semiconductor die overhangs the second semiconductor die.

37. The method of claim 35, further including depositing a second encapsulant over the third semiconductor die prior to depositing the first encapsulant.

38. The method of claim 30, further including:

mounting a third semiconductor die to the first semiconductor die; and

electrically connecting the third semiconductor die to the second semiconductor die.