Method and system for template assisted wafer bonding

• US 8,445,326 B2
• Filed: 06/19/2012
• Issued: 05/21/2013
• Est. Priority Date: 12/08/2010
• Status: Active Grant

• Current Assignee: Skoprios Technologies, Inc., Skorpios Technologies Inc.
• Original Assignee: Skorpios Technologies Inc.
• Inventors: Dallesasse, John, Krasulick, Stephen B.
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US13/527,394
• Publication Number:
  US 20120264256A1
• Time in Patent Office: 336 Days
• Field of Search: 438/63, 257/E21.513
• US Class Current: 438/113
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1204 Optical Diode
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 31/1876 Particular processes or apparatus for batch treatment of the devices
• CPC Class Codes: H01L 33/005 Processes
• CPC Class Codes: H01L 33/48 characterised by the semiconductor body packages
• CPC Class Codes: H01L 33/52 Encapsulations
• CPC Class Codes: H01S 5/0217 Removal of the substrate
• CPC Class Codes: H01S 5/026 Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers stabilisation of output H01S5/06

Abstract

A method of fabricating a composite semiconductor structure includes providing a substrate including a plurality of devices and providing a compound semiconductor substrate including a plurality of photonic devices. The method also includes dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method further includes providing an assembly substrate, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, aligning the substrate and the assembly substrate, joining the substrate and the assembly substrate to form a composite substrate structure, and removing at least a portion of the assembly substrate from the composite substrate structure.

Claims

1. A method of fabricating a composite semiconductor structure, the method comprising:

providing a substrate including a plurality of devices;

providing a compound semiconductor substrate including a plurality of photonic devices;

dicing the compound semiconductor substrate to provide a plurality of photonic dies, each die including one or more of the plurality of photonics devices;

providing an assembly substrate;

mounting the plurality of photonic dies on predetermined portions of the assembly substrate;

aligning the substrate and the assembly substrate;

joining the substrate and the assembly substrate to form a composite substrate structure; and

removing at least a portion of the assembly substrate from the composite substrate structure.

2. The method of claim 1 wherein the substrate comprises a GaN substrate.

3. The method of claim 1 wherein the plurality of devices comprise CMOS devices.

4. The method of claim 1 wherein the plurality of devices comprise at least one of a detector, a CCD, logic circuits, or emitter coupled logic circuits, BiCMOS circuits, NMOS circuits, or PMOS circuits.

5. The method of claim 1 wherein the compound semiconductor substrate comprises a III-V wafer.

6. The method of claim 5 wherein the plurality of photonic devices comprise at least one of InP photonic devices or GaN photonic devices.

7. The method of claim 1 wherein the compound semiconductor substrate comprises a II-VI wafer.

8. The method of claim 1 wherein the plurality of photonic devices include at least one of a laser, a detector, or a modulator.

9. The method of claim 8 wherein the plurality of photonic devices further include at least one of imaging optics, magnetic materials, birefringent materials, or non-linear optical materials.

10. The method of claim 1 wherein the compound semiconductor substrate further includes electronic devices.

11. The method of claim 10 wherein the electronic devices include at least one of HBTs, HEMTs, or FETs.

12. The method of claim 1 further comprising forming waveguide structures in another portion of the assembly substrate.

13. The method of claim 12 wherein the waveguide structures are operable to optically connect photonic dies of the plurality of photonic dies.

14. The method of claim 1 wherein providing the assembly substrate comprises:

oxidizing a silicon substrate;

implanting the oxidized silicon substrate to form an implant region; and

patterning the implanted substrate to form the predetermined portions.

15. A method of fabricating a composite semiconductor structure, the method comprising:

providing a substrate including a plurality of devices;

providing a compound semiconductor substrate including epitaxial layers;

dicing the compound semiconductor substrate to provide a plurality of compound semiconductor dies;

providing an assembly substrate;

mounting the plurality of compound semiconductor dies on predetermined portions of the assembly substrate;

aligning the substrate and the assembly substrate;

joining the substrate and the assembly substrate to form a composite substrate structure;

removing at least a portion of the assembly substrate from the composite substrate structure;

defining one or more photonic devices on the plurality of compound semiconductor dies; and

patterning electrical interconnects to the one or more photonic devices.

16. The method of claim 15 wherein the plurality of devices comprise CMOS devices.

17. The method of claim 15 wherein the compound semiconductor substrate comprises at least one of a III-V wafer or a II-VI wafer.

18. The method of claim 15 wherein the one or more photonic devices include at least one of a laser, a detector, or a modulator.

19. The method of claim 15 further comprising forming waveguide structures in another portion of the assembly substrate.

20. The method of claim 19 wherein the waveguide structures are operable to optically connect sets of the one or more photonic dies.