Devices and memory arrays including bit lines and bit line contacts

• US 8,446,011 B2
• Filed: 09/23/2011
• Issued: 05/21/2013
• Est. Priority Date: 04/13/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US13/243,510
• Publication Number:
  US 20120104463A1
• Time in Patent Office: 606 Days
• Field of Search: 257/758, 257/E21.682, 257/E21.69
• US Class Current: 257/758
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Each of the first bit lines of a device has an upper surface and a lower surface, with the upper surface being more outwardly located over a semiconductor surface than the lower surface. A second bit line of the device has an upper surface and a lower surface, with the upper surface thereof being more outwardly located over the semiconductor surface than the lower surface. The upper surface of the second bit line is more outwardly located over the semiconductor surface than the upper surfaces of the first bit lines. The first bit lines are each adjacent to the second bit line and the second bit line is configured to be selectively coupled to a memory cell other than memory cells to which the first bit lines are configured to be selectively coupled. The second bit line does not overlap any of the first bit lines.

Claims

1. A semiconductor device comprising:

first bit lines, wherein each of the first bit lines has an upper surface and a lower surface, with the upper surface being more outwardly located over a surface of a semiconductor than the lower surface; and

a second bit line, wherein the second bit line has an upper surface and a lower surface, with the upper surface thereof being more outwardly located over the surface of the semiconductor than the lower surface, and wherein the upper surface of the second bit line is more outwardly located over the surface of the semiconductor than the upper surfaces of the first bit lines,

wherein the first bit lines are each adjacent to the second bit line, the second bit line is configured to be selectively coupled to a memory cell other than memory cells to which the first bit lines are configured to be selectively coupled, and the second bit line does not overlap any of the first bit lines.

2. The semiconductor device of claim 1, wherein the lower surface of the second bit line is more outwardly located over the surface of the semiconductor than the lower surfaces of the first bit lines.

3. The semiconductor device of claim 1, wherein the lower surface of the second bit line is at about the elevation with respect to the surface of the semiconductor as the lower surfaces of the first bit lines.

4. The semiconductor device of claim 3, wherein the lower surface of the second bit line is at the same elevation with respect to the surface of the semiconductor as the lower surfaces of the first bit lines.

5. The semiconductor device of claim 1, wherein the lower surface of the second bit line is further away from the surface of the semiconductor than the upper surface of the first bit line.

6. The semiconductor device of claim 1 further comprising:

a second bit line contact electrically coupled to the second bit line and to the semiconductor, wherein the second bit line contact is interposed directly between the first bit lines.

7. A semiconductor device comprising:

a first bit line, wherein the first bit line has an upper surface and a lower surface, with the upper surface being more outwardly located over a surface of a semiconductor than the lower surface; and

a second bit line, wherein the second bit line has an upper surface and a lower surface, with the upper surface thereof being more outwardly located over the surface of the semiconductor than the lower surface, wherein the upper surface of the second bit line is more outwardly located over the surface of the semiconductor than the upper surface of the first bit line, wherein the first bit line is adjacent to the second bit line, and wherein the lower surface of the second bit line is at about the elevation with respect to the surface of the semiconductor as the lower surface of the first bit line.

8. The semiconductor device of claim 7, wherein the lower surface of the second bit line is at the same elevation with respect to the surface of the semiconductor as the lower surface of the first bit line.

9. A semiconductor device, comprising:

first bit line plugs at a first cross-sectional location and second bit line plugs at a second cross-sectional location;

a plurality of first bit lines at both the first and second cross-sectional locations, wherein the first bit lines contact the first bit line plugs at the first cross-sectional location but do not contact the second bit line plugs at the second cross-sectional location;

a plurality of second bit lines at both the first and second cross-sectional locations, wherein the second bit lines contact the second bit line plugs at the second cross-sectional location but do not contact the first bit line plugs at the first cross-sectional location, wherein an upper surface of the second bit lines at both the first and second cross-sectional locations is more outwardly located over a surface of a semiconductor than an upper surface of the first bit lines, and wherein each of the plurality of bit lines can be selectively coupled to a different memory cell.

10. The semiconductor device of claim 9 wherein a bottom surface of the second bit lines at the first cross-sectional location is more outwardly located over the surface of the semiconductor than an upper surface of the first bit lines at the first cross-sectional location.

11. The semiconductor device of claim 9 wherein at least one second bit line is interposed between two adjacent first bit lines at the second cross-sectional location, but the at least one second bit line is not interposed between the two adjacent first bit lines at the first cross-sectional location.

12. The semiconductor device of claim 9 further comprising:

the second bit lines comprising;

a first conductive layer which contacts the second bit line plugs at the second cross-sectional location;

a second conductive layer which contacts the first conductive layer at the second-cross-sectional location, wherein a bottom surface of the second conductive layer at the first cross-sectional location is more outwardly located over the surface of the semiconductor than an upper surface of the first bit lines at the first cross-sectional location.

13. A memory array, comprising:

a first conductive bit line comprising at least one first conductive layer that can be selectively electrically coupled with a first plurality of memory cells; and

second conductive bit lines, each of which is adjacent to the first conductive bit line, comprising at least one second conductive layer, wherein a first one of the second conductive bit lines can be selectively electrically coupled with a second plurality of memory cells, wherein a second one of the second conductive bit lines can be selectively electrically coupled with a third plurality of memory cells, wherein the at least one second conductive layer is a different layer than the at least one first conductive layer, wherein the first plurality of memory cells are not either of the second and third plurality of memory cells, and wherein each of the second conductive bit lines do not overlap another bit line.

14. The memory array of claim 13, wherein the memory array comprises a portion of a NAND memory device.

15. The memory array of claim 13 further comprising:

at least a first bit line contact plug which electrically couples the first conductive bit line to a first conductively doped region of a semiconductor; and

at least a second bit line contact plug which electrically couples one of the second conductive bit lines to a second conductively doped region of the semiconductor.

16. The memory array of claim 15 wherein the first and second bit line contact plugs are staggered.

17. An electronic device comprising:

at least one semiconductor device having a cross section comprising;

first bit lines, wherein each of the first bit lines has an upper surface and a lower surface, with the upper surfaces being more outwardly located over a surface of a semiconductor than the lower surfaces; and

a second bit line, wherein the second bit line has an upper surface and a lower surface, with the upper surface thereof being more outwardly located over the surface of the semiconductor than the lower surface,

wherein the upper surface of the second bit line is more outwardly located over the surface of the semiconductor than the upper surfaces of the first bit lines, each of the first bit lines is adjacent to the second bit line, and wherein each of the first bit lines is associated with a memory cell other than a memory cell associated with the second bit line.

18. The electronic device of claim 17, wherein the second bit line is associated with a memory cell other than a memory cell associated with one of the first bit lines.

19. A memory array, comprising:

a first conductive bit line comprising a first conductive layer that can be selectively electrically coupled with a first plurality of memory cells; and

second conductive bit lines comprising a second conductive layer different from the first conductive layer, wherein a first one of the second conductive bit lines can be selectively electrically coupled with a second plurality of memory cells, wherein a second one of the second conductive bit lines can be selectively electrically coupled with a third plurality of memory cells, wherein the first conductive bit line is adjacent to each of the second conductive bit lines, wherein the first plurality of memory cells are not either of the second and third plurality of memory cells, and wherein each of the second conductive bit lines do not overlap another bit line.

20. The memory array of claim 19 wherein the first plurality of memory cells and the first conductive bit line are coupled through at least one select transistor.

21. The memory array of claim 19 further comprising:

at least a first bit line contact plug which electrically couples the first conductive bit line to a first conductively doped region of a semiconductor; and

at least a second bit line contact plug which electrically couples one of the second conductive bit lines to a second conductively doped region of the semiconductor.

22. A memory array comprising:

a first conductive layer comprising a first conductive bit line that can be selectively electrically coupled with a first plurality of memory cells; and

a second conductive layer comprising second conductive bit lines, wherein a first one of the second conductive bit lines can be selectively electrically coupled with a second plurality of memory cells, wherein a second one of the second conductive bit lines can be selectively electrically coupled with a third plurality of memory cells, wherein the first conductive bit line is adjacent to each of the second conductive bit lines, wherein the first plurality of memory cells are not either of the second and third plurality of memory cells, and wherein each of the second conductive bit lines do not overlap another bit line.

23. The memory array of claim 22 wherein the first plurality of memory cells and the first conductive bit line are coupled through at least one select transistor.

24. The memory array of claim 22 wherein the memory array comprises a portion of a NAND memory device.

25. The memory array of claim 22 further comprising:

at least a first bit line contact plug which electrically couples the first conductive bit line to a first conductively doped region of a semiconductor; and

at least a second bit line contact plug which electrically couples one of the second conductive bit lines to a second conductively doped region of the semiconductor.