Reconfigurable engineering change order base cell

• US 8,446,176 B1
• Filed: 12/15/2011
• Issued: 05/21/2013
• Est. Priority Date: 12/15/2011
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Yang, Jianan, Jamison, Stephen G., Hutchinson, Darrin L.
• Primary Examiner(s): Ismail, Shawki
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US13/326,556
• Time in Patent Office: 523 Days
• Field of Search: 326/103, 326/104, 326/112, 326/101, 257/401, 257/203, 716/10, 716/12, 716/19
• US Class Current: 326/103
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

An integrated circuit ECO base cell module is formed with PMOS and NMOS gate electrode structures and power supply lines that are electrically separated from one another up to the second metal (M2) layer in a fixed circuit structure that may be reconfigured with one or more conductor elements formed above the M2 layer to form a predetermined circuit function.

Claims

1. A configured base cell module comprising:

a plurality of base cells, each having a fixed circuit structure through a second metal (M2) layer and comprising;

an n-well and a p-well formed in a substrate,

PMOS and NMOS gate electrode structures formed over the n-well and p-well and electrically separated from another up to the second metal (M2) layer,

P+ implant and N+ implant regions formed adjacent to the PMOS and NMOS gate electrode structures in the n-well and p-well, respectively, and

first and second power supply lines formed over the n-well and p-well and electrically separated from another up to the second metal (M2) layer; and

one or more conductor elements formed over a first base cell above the M2 layer to configure the first base cell to provide a predetermined circuit function.

2. The configured base cell module of claim 1, where the predetermined circuit function is an inverter circuit.

3. The configured base cell module of claim 1, where the predetermined circuit function is a buffer circuit.

4. The configured base cell module of claim 1, where the predetermined circuit function is a multiplexer circuit.

5. The configured base cell module of claim 1, where the predetermined circuit function is an AND-OR-Invert (AOI) logic gate circuit.

6. The configured base cell module of claim 1, where the predetermined circuit function is a NAND logic gate circuit, NOR logic gate circuit, XOR logic gate circuit, latch circuit, or de-coupling capacitor circuit.

7. The configured base cell module of claim 1, further comprising a second base cell having the fixed circuit structure through the second metal (M2) layer without one or more conductor elements formed over the second base cell above the M2 layer to configure the second base cell to provide a predetermined circuit function.

8. The configured base cell module of claim 1, where the fixed circuit structure comprises:

at least one PMOS transistor formed with a PMOS gate electrode structure and having electrically separate conductor paths to gate, source and drain terminals of the PMOS transistor formed up to the second metal (M2) layer; and

at least one NMOS transistor formed with an NMOS gate electrode structure and having electrically separate conductor paths to gate, source and drain terminals of the NMOS transistor formed up to the second metal (M2) layer.

9. The configured base cell module of claim 1, where the fixed circuit structure comprises:

a plurality of PMOS transistors formed with PMOS gate electrode structures and connected together and to the first power supply line at or below the second metal (M2) layer to form a PMOS NAND logic gate circuit and/or PMOS NOR logic gate circuit; and

a plurality of NMOS transistors formed with NMOS gate electrode structures and connected together and to the second power supply line at or below the second metal (M2) layer to form a NMOS NAND logic gate circuit and/or NMOS NOR logic gate circuit.

10. The configured base cell module of claim 1, where the plurality of base cells comprises a first base cell configured with one or more conductor elements formed above the M2 layer to provide a first circuit function, and a second base cell configured with one or more conductor elements formed above the M2 layer to provide a second different circuit function.

11. A programmed base cell module comprising:

at least one PMOS transistor comprising a PMOS gate electrode and p-type source and drain regions with a fixed conductor path to the PMOS gate electrode formed up to a second metal (M2) layer;

at least one NMOS transistor comprising an NMOS gate electrode and n-type source and drain regions with a fixed conductor path to the NMOS gate electrode formed up to the second metal (M2) layer, where the NMOS gate electrode is electrically disconnected from the PMOS gate electrode up to the second metal (M2) layer;

a first reference voltage conductor line with one or more first conductor paths formed up to the second metal (M2) layer;

a second reference voltage conductor line with one or more second conductor paths formed up to the second metal (M2) layer, where the second reference voltage conductor line is electrically disconnected from the first reference voltage conductor line up to the second metal (M2) layer; and

one or more conductor elements formed above the second metal (M2) layer;

where the programmed base cell module has a fixed circuit structure through the second metal (M2) layer and where the one or more conductor elements formed above the second metal (M2) layer program the fixed circuit structure to form a predetermined circuit function.

12. The programmed base cell module of claim 11, where the one or more conductor elements comprise patterned conductor layers formed in one or more metal layers above the second metal (M2) layer to form an inverter circuit, buffer circuit, a multiplexer circuit, an AND-OR-Invert (AOI) logic gate circuit, a NAND logic gate circuit, a NOR logic gate circuit, an XOR logic gate circuit, a latch circuit, or a de-coupling capacitor circuit.

13. The programmed base cell module of claim 11, where the fixed circuit structure comprises one or more PMOS transistors and one or more NMOS transistors, each having gate, source and drain terminals that are electrically separate from one another up to the second metal (M2) layer.

14. The programmed base cell module of claim 11, where the fixed circuit structure comprises:

a plurality of PMOS transistors formed with PMOS gate electrodes and connected together and to the first reference voltage conductor line at or below the second metal (M2) layer to form a PMOS NAND logic gate circuit and/or a PMOS NOR logic gate circuit; and

a plurality of NMOS transistors formed with NMOS gate electrodes and connected together and to the second power supply line at or below the second metal (M2) layer to form a NMOS NAND logic gate circuit and/or a NMOS NOR logic gate circuit, where the NMOS gate electrodes are electrically separate from the PMOS gate electrodes.

15. A method for making an integrated circuit device comprising:

placing one or more functional cells and one or more base cells in a preliminary layout design, where each base cell comprises a plurality of electrically separate gate electrode structures in a fixed circuit structure through the second metal (M2) layer;

routing the one or more functional cells according to the preliminary layout design;

altering at least one metal layer above the second metal (M2) layer in one or more base cells to form one or more programmed functional cells, each having a predetermined circuit function;

re-routing the one or more functional cells to be integrated with the one or more programmed functional cells to produce a device layout design; and

making an integrated circuit device using the device layout design.

16. The method of claim 15, where altering at least one metal layer comprises altering a metal conductor and/or via layer above the second metal (M2) layer.

17. The method of claim 15, where the one or more base cells have the same features or element configurations as the one or more functional cells up through the second metal (M2) layer.

18. The method of claim 15, where the one or more base cells have the same layout pitch as the one or more functional cells up through the second metal (M2) layer.

19. The method of claim 15, where each base cell comprises an n-well and p-well formed in a substrate;

PMOS and NMOS gate electrode structures formed over the n-well and p-well and electrically separated from another up to the second metal (M2) layer; and

P+ implant and N+ implant regions formed in the n-well and p-well, respectively.

20. The method of claim 15, where each base cell having the fixed circuit structure comprises one or more PMOS transistors and one or more NMOS transistors, each having gate, source and drain terminals that are electrically separate from one another up to the second metal (M2) layer.

21. The method of claim 15, where each base cell having the fixed circuit structure comprises:

a plurality of PMOS transistors formed with PMOS gate electrode structures and connected together and to the first power supply line at or below the second metal (M2) layer to form a PMOS NAND logic gate circuit and/or PMOS NOR logic gate circuit; and

a plurality of NMOS transistors formed with NMOS gate electrode structures and connected together and to the second power supply line at or below the second metal (M2) layer to form a NMOS NAND logic gate circuit and/or NMOS NOR logic gate circuit.