Apparatus and method to hold PLL output frequency when input clock is lost

• US 8,446,193 B2
• Filed: 05/02/2011
• Issued: 05/21/2013
• Est. Priority Date: 05/02/2011
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Zhang, Ben-yong, Christiansen, Tom, Schell, Christopher Andrew
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/099,253
• Publication Number:
  US 20120280735A1
• Time in Patent Office: 750 Days
• Field of Search: 327/147, 327/156
• US Class Current: 327/156
• CPC Class Codes: H03L 2207/08 Modifications of the phase-locked loop for ensuring constant frequency when the power supply fails or is interrupted, e.g. for saving power
• CPC Class Codes: H03L 7/146 by using digital means for generating the oscillator control signal H03L7/141, H03L7/143 take precedence

Abstract

A clock conditioning circuit including a phase detector circuit configured to provide an analog tuning signal indicative of a phase relationship between a reference clock to be conditioned and a generated clock. The controlled oscillator is configured to produce the generated clock, with the generated clock having an output frequency adjustable in response to an analog tuning signal applied to a control signal input of the controlled oscillator. Converter circuitry is provided to produce a digital representation of the analog tuning signal when the mode control circuitry is in a tracking mode. In the event the reference clock is lost, the mode control circuitry switches to a holdover mode so as to provide an analog holdover signal to the control signal input based upon the digital representations produced just prior to the loss of the reference clock.

Claims

1. A clock conditioning circuit comprising:

a phase detector circuit configured to provide an analog tuning signal indicative of a phase relationship between a reference clock to be conditioned and a generated clock;

a controlled oscillator configured to produce the generated clock, with the generated clock having an output frequency adjustable in response to an analog tuning signal applied to a control signal input of the controlled oscillator;

mode control circuitry switchable between at least two modes, including a tracking mode and a holdover mode, with the mode control circuitry operating in the tracking mode to couple the analog tuning signal to the control signal input of the controlled oscillator and with the mode control circuitry operating in the holdover mode to couple an analog holdover signal to the control signal input of the controlled oscillator; and

converter circuitry configured to produce a digital representation of the analog tuning signal when the mode control circuitry is in the tracking mode and to provide the analog holdover signal to the control signal input when the mode control circuitry is in the holdover mode, with the analog holdover signal being based upon one of the digital representations produced when the mode control circuitry was in the tracking mode.

2. The clock conditioning circuit of claim 1 wherein the mode control circuitry operating in the holdover mode operates to isolate the output of the phase detector from the control signal input of the controlled oscillator.

3. The clock conditioning circuit of claim 2 wherein the phase detector circuit includes a phase measurement circuit which receives the reference clock and the generated clock and produces at least one digital output signal having a pulse width relating to a phase difference between the reference clock and the generated clock.

4. The clock conditioning circuit of claim 3 where the phase detector further includes a charge pump circuit followed by a low pass filter, with the charge pump circuit delivering a charge to the low pass filter, with the charge being determined by the pulse width of the digital output signal of the phase measurement circuit.

5. The clock conditioning circuit of claim 4 further including a first frequency divider circuit having an input that receives the generated clock and an output coupled to an input of the phase detector circuit.

6. The clock conditioning circuit of claim 5 further including a second frequency divider circuit having an input that receives the reference clock and an output coupled to another input of the phase detector circuit.

7. The clock conditioning circuit of claim 1 further including a clock failure detection circuit which causes the mode control circuitry to switch to the holdover mode after a reference clock has failed.

8. The clock conditioning circuit of claim 1 wherein the converter circuitry includes an analog to digital converter circuit having an analog input coupled to the control signal input when the mode control circuitry is in the tracking mode, with the analog to digital converter operating to produce the digital representation of the analog tuning signal.

9. The clock conditioning circuit of claim 8 wherein the converter circuitry includes a digital to analog converter circuit which produces the analog holdover signal when the mode control circuitry is in the holdover mode based upon a digital input produced by the analog to digital converter circuit when the mode control circuitry was in a previous tracking mode.

10. The clock conditioning circuit of claim 9 wherein the analog to digital converter includes the digital to analog converter.

11. The clock conditioning circuit of claim 1 wherein the controlled oscillator is a voltage controlled oscillator.

12. A method of conditioning a clock signal comprising:

producing an analog tuning signal indicative of a phase difference between a reference clock to be conditioned and a generated clock;

providing a controlled oscillator to produce the generated clock, with the generated clock being generated in response to an analog signal applied to a control input of the controlled oscillator;

operating in a tracking mode of operation where the analog tuning signal is coupled to the control input of the controlled oscillator;

generating a digital representation of the analog tuning signal during the tracking mode of operation; and

switching to a holdover mode of operation where the analog tuning signal is replaced with an analog holdover signal, with the analog holdover signal being generated based upon the digital representation of the analog tuning signal generated during the previous tracking mode of operation.

13. The method of claim 12 wherein the switching to the holdover mode of operation is in response to a loss of the reference clock.

14. The method of claim 13 further including switching back to the tracking mode of operation from the holdover mode of operation in response to a return of the reference clock.

15. The method of claim 14 wherein the analog holdover signal is generated using a digital to analog converter and wherein the digital representation of the analog tuning signal is produced using the digital to analog converter.

16. The method of claim 12 wherein the step of producing an analog tuning signal includes dividing a frequency of the generated clock.

17. The method of claim 12 wherein the step of producing an analog tuning signal includes dividing a frequency of the reference clock.

18. A clock conditioning circuit for use with a controlled oscillator configured to produce a generated clock, with the generated clock having an output frequency adjustable in response to an analog tuning signal applied to a control signal input of the controlled oscillator, said clock conditioning circuit comprising:

a phase detector circuit configured to provide, when a controlled oscillator is present, the analog tuning signal indicative of a phase relationship between a reference clock to be conditioned and the generated clock;

mode control circuitry switchable between at least two modes, including a tracking mode and a holdover mode, so that when a controlled oscillator is present and the mode control circuitry is operating in the tracking mode, the analog tuning signal is coupled to the control signal input of the controlled oscillator and so that when a controlled oscillator is present and the mode control circuitry is operating in the holdover mode, an analog holdover signal is coupled to the control signal input of the controlled oscillator; and

converter circuitry configured to produce a digital representation of the analog tuning signal when the mode control circuitry is in the tracking mode and to provide the analog holdover signal to the control signal input when the mode control circuitry is in the holdover mode, with the analog holdover signal being based upon one of the digital representations produced when the mode control circuitry was in the tracking mode.

19. The clock conditioning circuit of claim 18 wherein the mode control circuitry operating in the holdover mode operates to isolate the output of the phase detector from the control signal input of the controlled oscillator when a controlled oscillator is present.

20. The clock conditioning circuit of claim 19 wherein the phase detector circuit includes a phase measurement circuit which receives the reference clock and the generated clock when a controlled oscillator is present and produces at least one digital output signal having a pulse width relating to a phase difference between the reference clock and the generated clock.

21. The clock conditioning circuit of claim 20 where the phase detector further includes a charge pump circuit, with the charge pump circuit delivering a total charge to an output of the charge pump circuit determined by the pulse width of the digital output signal of the phase measurement circuit.

22. The clock conditioning circuit of claim 21 further including a first frequency divider circuit having an input that receives the generated clock when a controlled oscillator is present and an output coupled to an input of the phase detector circuit.

23. The clock conditioning circuit of claim 22 further including a second frequency divider circuit having an input that receives the reference clock and an output coupled to another input of the phase detector circuit.

24. The clock conditioning circuit of claim 18 further including a clock failure detection circuit which causes the mode control circuitry to switch to the holdover mode after a reference clock has failed.