Nonvolatile memory device and related programming method

• US 8,446,766 B2
• Filed: 09/27/2012
• Issued: 05/21/2013
• Est. Priority Date: 03/25/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Ki Tae, Kang, Myoung Gon
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US13/628,244
• Publication Number:
  US 20130021847A1
• Time in Patent Office: 236 Days
• Field of Search: None
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic component selects a memory block to be programmed based on program/erase cycles of the memory blocks, and selects a program rule used to program the regions of the selected memory block.

Claims

1. A memory system, comprising:

a nonvolatile memory device including a storage space, the storage space having a plurality of NAND strings and divided into at least two or more storage regions; and

a controller configured to manage an erase/program cycle table in which wearing levels of the at least two or more storage regions are stored,

wherein when a program operation on the storage space is requested, the controller selects one of the at least two or more storage regions in the storage space based on wearing levels stored in the erase/program cycle table, the selected storage region having a lowest wearing level.

2. The memory system of claim 1, wherein each of the plurality of NAND strings is divided into the at least two or more storage regions.

3. The memory system of claim 1, wherein the storage space is a memory block of the nonvolatile memory device and the at least two or more storage regions are sub regions of the memory block.

4. The memory system of claim 1, wherein the nonvolatile memory device further comprises another storage space divided into at least two or more storage regions and the controller manages the erase/program cycle table such that wearing levels of the storage spaces are further stored.

5. The memory system of claim 3, wherein the erase/program cycle table is stored at the nonvolatile memory device and is loaded from the nonvolatile memory device at power-up.

6. The memory system of claim 5, wherein the wearing levels are determined according to at least one of a program count or an erase count of each of the at least two or more storage regions.

7. The memory system of claim 1, wherein the storage space stores single bit data per cell or multi-bit data per cell.

8. The memory system of claim 4, wherein the controller controls the nonvolatile memory device to select a storage space having a low program or erase count among the storage spaces and to program the selected storage space using a rule that requires the at least two or more storage regions of the selected storage space to be programmed in an order beginning with a region having a lowest program or erase count.

9. A program method of a memory system which includes a nonvolatile memory device including a plurality of storage spaces;

and a controller controlling the nonvolatile memory device, comprising;

receiving a write request;

selecting one to be programmed of the plurality of storage spaces, each storage space including a plurality of NAND strings and divided into at least two or more storage regions; and

selecting one of the at least two or more storage regions in the selected storage space based on wearing levels stored in an erase/program cycle table in which wearing levels of the at least two or more storage regions of each storage space are stored, the selected storage region having a lowest wearing level.

10. The program method of claim 9, wherein each of the plurality of NAND strings is divided into the at least two or more storage regions.

11. A nonvolatile memory device, comprising:

a memory cell array including a plurality of memory blocks;

a row decoder connected to the memory cell array and configured to select the plurality of memory blocks;

a voltage generator configured to generate word line voltages to be supplied to the memory cell array through the row decoder; and

a read/write circuit configured to operate as a write driver at a program operation and as a sense amplifier at a read operation,

wherein each of the plurality of memory blocks is divided into at least two or more storage regions and includes a plurality of NAND strings, the memory cell array stores an erase/program cycle table including program or erase counts of the at least two or more storage regions of each memory block, and the erase/program cycle table is used to select one, having a lowest wearing level, of the at least two or more storage regions in each memory block.

12. The nonvolatile memory device of claim 11, wherein the erase/program cycle table is provided to a controller which controls a wear leveling of the nonvolatile memory device.

13. The nonvolatile memory device of claim 11, wherein each of the plurality of NAND strings is divided into the at least two or more storage regions.