Multi-rank partial width memory modules

• US 8,446,781 B1
• Filed: 03/02/2012
• Issued: 05/21/2013
• Est. Priority Date: 11/13/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Smith, Michael John Sebastian
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US13/411,489
• Time in Patent Office: 445 Days
• Field of Search: 365/189.03
• US Class Current: 365/189.03
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

A system is provided for multi-rank, partial-width memory modules. A memory controller is provided. Additionally, a memory bus is provided. Further, a memory module with a plurality of ranks of memory circuits is provided, the memory module including a first number of data pins that is less than a second number of data pins of the memory bus.

Claims

1. A system, comprising:

a memory controller configured to address a number of ranks of memory, the number of ranks being greater than one, each rank having a memory controller rank width;

a memory bus coupled to the memory controller, the memory bus comprising a data bus and a control bus, the data bus having a first number of data signals; and

a plurality of memory modules, wherein

each memory module is coupled to the memory controller through the memory bus,

each memory module has the same number of ranks of memory as the memory controller is configured to address, each rank on each memory module having a module rank width that is less than the memory controller rank width,

each memory module has a number of data pins coupled to the data bus that is equal to the module rank width, the data pins of the plurality of memory modules each being coupled to a different one of the data signals of the data bus, and

a sum of the module rank widths of the plurality of memory modules is equal to the memory controller rank width.

2. The system of claim 1, wherein each memory module further comprises:

a buffer chip coupled to a corresponding memory circuit of a first rank of the number of ranks and the data bus,

wherein data pins of the corresponding memory circuit of the first rank are connected to a first set of data pins of the buffer chip, and

wherein a subset of the data pins of each memory module are connected to a second set of data pins of the respective buffer chip.

3. The system of claim 2, wherein the buffer chip is further coupled to a corresponding memory circuit of a second rank of the number of ranks,

wherein data pins of the corresponding memory circuit of the second rank are connected to a third set of data pins of the buffer chip, such that a loading of multiple ranks of the memory modules on the data bus appears to the memory controller as a loading of a reduced number of ranks.

4. The system of claim 2, wherein the buffer chip is configured to transform a first data rate associated with memory circuits of the memory modules to a second, different data rate.

5. The system of claim 2, wherein the buffer chip is configured to transform a first data width associated with memory circuits of the memory modules to a second, different data width.

6. The system of claim 2, wherein a number of the first set of data pins of the buffer chip coupled to the corresponding memory circuit of the first memory rank are more than a number of the second set of data pins of the buffer chip coupled to the memory data bus.

7. The system of claim 2, wherein a number of the first set of data pins of the buffer chip coupled to the corresponding memory circuit of the first memory rank are equal to a number of the second set of data pins of the buffer chip coupled to the memory data bus.

8. The system of claim 1, wherein the plurality of memory modules include two memory modules, and wherein the module rank width of each of the two memory modules is half of the memory controller rank width.

9. The system of claim 8, wherein the memory controller is configured to address four ranks of memory.

10. The system of claim 1, wherein the plurality of memory modules include three memory modules, and wherein the module rank width of each of the two memory modules is one third of the memory controller rank width.

11. The system of claim 10, wherein the memory controller is configured to address six ranks of memory.

12. The system of claim 1, wherein the control bus includes a plurality of chip select signals coupled to the memory controller and the plurality of memory modules, and wherein a number of the plurality of chip select signals are equal to the number of ranks of memory that the memory controller is configured to address.

13. The system of claim 12, wherein each memory module further comprises:

a register chip configured to;

receive a chip select signal of the plurality of chip select signals from the memory controller to access a particular rank of the ranks; and

assert a corresponding chip select signal to memory circuits of the particular rank.

14. A system, comprising:

a memory controller configured to address a number of ranks of memory, the number of ranks being greater than one, each rank having a memory controller rank width;

a memory bus coupled to the memory controller, the memory bus comprising a data bus and a control bus, the data bus having a first number of data signals; and

two memory modules, wherein

each memory module is coupled to the memory controller through the memory bus,

each memory module has the same number of ranks of memory as the memory controller is configured to address, each rank on each memory module having a module rank width that is half of the memory controller rank width,

each memory module has a number of data pins coupled to the data bus that is equal to the module rank width, the data pins of the two memory modules each being coupled to a different one of the data signals of the data bus, and

a sum of the module rank widths of the two memory modules is equal to the memory controller rank width.

15. The system of claim 14, wherein each memory module further comprises:

a buffer chip coupled to a corresponding memory circuit of a first rank of the number of ranks, a corresponding memory circuit of a second rank of the number of ranks, and the data bus,

wherein data pins of the corresponding memory circuit of the first rank are connected to a first set of data pins of the buffer chip,

wherein data pins of the corresponding memory circuit of the second rank are connected to a second set of data pins of the buffer chip, and

wherein a subset of the data pins of each memory module are connected to a third set of data pins of the respective buffer chip, such that a loading of multiple ranks of the memory modules on the data bus appears to the memory controller as a loading of a reduced number of ranks.

16. The system of claim 15, wherein the buffer chip is configured to transform a first data rate associated with memory circuits of the memory modules to a second, different data rate.

17. The system of claim 15, wherein the buffer chip is configured to transform a first data width associated with memory circuits of the memory modules to a second, different data width.

18. The system of claim 15, wherein a number of the first set of data pins of the buffer chip coupled to the corresponding memory circuit of the first memory rank are more than a number of the third set of data pins of the buffer chip coupled to the memory data bus.

19. The system of claim 15, wherein a number of the first set of data pins of the buffer chip coupled to the corresponding memory circuit of the first memory rank are equal to a number of the third set of data pins of the buffer chip coupled to the memory data bus.

20. The system of claim 14,

wherein the control bus includes a plurality of chip select signals coupled to the memory controller and the two memory modules,

wherein a number of the plurality of chip select signals are equal to the number of ranks of memory that the memory controller is configured to address, and

wherein each of the two memory module further comprises:

a register chip configured to;

receive a chip select signal of the plurality of chip select signals from the memory controller to access a particular rank of the ranks; and

assert a corresponding chip select signal to memory circuits of the particular rank.