PCI express enhancements and extensions

• US 8,447,888 B2
• Filed: 12/09/2011
• Issued: 05/21/2013
• Est. Priority Date: 11/02/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ajanovic, Jasmin, Wagh, Mahesh, Sethi, Prashant, Das Sharma, Debendra, Harriman, David, Rosenbluth, Mark, Bhatt, Ajay, Barry, Peter, Rodgers, Scott Dion, Vasudevan, Anil, Muthrasanallur, Sridhar, Akiyama, James, Blankenship, Robert, Falik, Ohad, Mendelson, Abraham, Pardo, Ilan, Tamari, Eran, Weissmann, Eliezer, Shamia, Doron
• Primary Examiner(s): Alrobaye, Idriss N
• Assistant Examiner(s): MARTINEZ, DAVID E
• Application Number:
  US13/316,349
• Publication Number:
  US 20120089750A1
• Time in Patent Office: 529 Days
• Field of Search: None
• US Class Current: 710/5
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Claims

1. An apparatus comprising:

receiving logic in a first device, the receiving logic configured to receive a first packet referencing a memory access operation on a serial, point-to-point interconnect, wherein the first packet is to include a reference to an address and a length field capable to hold a length to indicate a number of cache lines in a block, a stride field capable to hold a stride to indicate an offset to a start of a next block, and a block count field capable to hold a block count to indicate a number of blocks to prefetch; and

fetch logic configured to;

initate a fetch request of an element at the address in response to the receiving logic receiving the first packet and the first packet referencing the memory access operation and the address; and

initiate a prefetch of an additional element in response to receiving the first packet based on one or more of the length field, the stride field, or the count field, wherein the first packet is associated with an access control hint comprising a locality hint and that is to be indicative of a location at which prefetched elements are to be cached.

2. The method of claim 1, wherein the first packet is a prefetch message, and wherein the access control hint to be selected from a group consisting of an evict hint, an intent to read only hint, intent to write only hint, intent to read and write hint, and a direct input/output (DIO) hint.

3. The method of claim 2, wherein the address is a starting address.

4. The method of claim 3, further comprising:

determining the additional element to be prefetched based on the starting address and each of the length field, the stride field, and the count field.

5. The apparatus of claim 1, wherein a prefetch hint is provided as part of the first packet, and wherein the prefetch hint is to include a reference to bias fetching of additional elements.

6. The apparatus of claim 5, wherein the prefetch hint relates to an activity for reading ahead for particular data.

7. The apparatus of claim 5, wherein the prefetch hint relates to an activity for maintaining coherent copies of prefetched cache lines.

8. The apparatus of claim 5, wherein the prefetch hint references another element to be prefetched, along with an interleave bit to indicate an order to fetch additional cache lines.

9. The apparatus of claim 5, wherein the prefetch hint includes a temporal use indication to indicate when a particular device will issue a request for a block and that influences a cache allocation associated with a root controller.

10. The apparatus of claim 1, wherein a temporal hint is provided as part of the first packet, and wherein the temporal hint is to indicate a device'"'"'s access intention to bias caching activities associated with a plurality of elements.

11. The apparatus of claim 1, wherein the locality hint is to indicate if the prefetched elements are to be cached at a root controller cache, a device cache, a system memory cache, or processor cache.

12. A system comprising:

a first device including,

receiving logic in a first device, the receiving logic configured to receive a first packet referencing a memory access operation on a serial, point-to-point interconnect, wherein the first packet is to include a reference to an address to be associated with a memory location in a system memory a length field capable to hold a length to indicate a number of cache lines in a block, a stride field capable to hold a stride to indicate an offset to a start of a next block, and a block count field capable to hold a block count to indicate a number of blocks to prefetch; and

fetch logic configured to;

initiate a fetch request of an element at the address in response to the receiving logic receiving the first packet and the first packet referencing the memory access operation and the address; and

initiate a prefetch of an additional element in response to receiving the first packet based on one or more of the length field, the stride field, or the count field, wherein the first packet is associated with an access control hint comprising a locality hint and that is to be indicative of a location at which prefetched elements are to be cached.

13. The system of claim 12, wherein the first packet is a prefetch message, and wherein the access control hint to be selected from a group consisting of an evict hint, an intent to read only hint, intent to write only hint, intent to read and write hint, and a direct input/output (DIO) hint.

14. The system of claim 13, wherein the address is a starting address.

15. The system of claim 14, wherein the system is further configured for:

determining the additional element to be prefetched based on the starting address and the plurality of prefetch parameters.