PCI-E extended reach with receive detect circuitry

• US 8,447,892 B1
• Filed: 09/27/2007
• Issued: 05/21/2013
• Est. Priority Date: 09/27/2007
• Status: Active Grant

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Felton, Mickey S., Julian, Simba M.
• Primary Examiner(s): Tsai, Henry
• Application Number:
  US11/862,491
• Time in Patent Office: 2,063 Days
• Field of Search: None
• US Class Current: 710/15
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004

Abstract

A type one protocol device transmitter performs a detection function to detect attached type one protocol receivers. The detection function operates such that receivers having type two termination are not detected as type one protocol receivers. A type two protocol device receiver has type two termination. Logic is coupled between the type two protocol device receiver and the type one protocol device transmitter so that the type one protocol device transmitter detection function detects the type two protocol device receiver as a type one protocol receiver. The type one protocol device can be a PCI-E device, and the type two protocol device can be a SAS/SATA device.

Claims

1. An Apparatus comprising:

a type one protocol device physical layer transmitter that performs a physical layer detection function to detect type one protocol device physical layer receivers attached via an interconnect, said detection function operating such that in response to a signal sent from the physical layer detection function, physical layer receivers having type one physical layer termination cause the interconnect to charge and physical layer receivers having type two physical layer termination appear as an open circuit to said physical layer detection function;

a type two protocol device physical layer receiver having type two physical layer termination, the type two protocol device physical layer receiver being connected to the type one protocol device physical layer transmitter by at least one differential signal pair; and

logic functional such that when said logic is coupled to the at least one differential signal pair between the type two protocol device physical layer receiver and the type one protocol device physical layer transmitter, the type one protocol device physical layer transmitter detection function detects the type two protocol device physical layer receiver as a type one protocol device physical layer receiver by causing the at least one differential signal to charge in order to indicate that the type two protocol device physical layer receiver is a valid type one protocol device physical layer receiver and to enable the type two protocol device physical layer receiver to functionally receive type one protocol communications directly from the type one protocol device physical layer transmitter over the at least one differential signal pair.

2. The Apparatus of claim 1 wherein the type one protocol device physical layer transmitter is a PCI-E device physical layer transmitter.

3. The Apparatus of claim 2 wherein the type two protocol device physical layer receiver is a SAS/SATA device physical layer receiver.

4. The Apparatus of claim 3 wherein the type one protocol device physical layer transmitter and type two protocol device physical layer receiver are differential, and wherein the logic further comprises for each signal line of the at least one differential signal pair:

a ferrite and resistor in parallel.

5. The Apparatus of claim 1, wherein the type two protocol device physical layer receiver includes buffers capable of buffering signals received from the type one protocol device physical layer transmitter.

6. The Apparatus of claim 1, wherein the type two protocol device physical layer receiver extends the interconnect to another interconnect for carrying the signals received from the type one protocol device physical layer transmitter.

7. The Apparatus of claim 1, wherein the logic, by causing the at least one differential signal pair to charge, enables the type two protocol device physical layer receiver to perform link training with the type one protocol device physical layer transmitter.

8. An Apparatus comprising:

logic coupled to a differential signal pair that connects a PCI-E physical layer transmitter of a PCI-E device to a SAS/SATA physical layer receiver, the logic causing the PCI-E physical layer transmitter to recognize the SAS/SATA physical layer receiver as a valid PCI-E receiver by causing the differential signal pair to charge upon transmission of a PCI-E physical layer transmission to indicate to the PCI-E device that the SAS/SATA physical layer receiver is a valid PCI-E receiver and to enable the SAS/SATA physical layer receiver to functionally receive communications directly from the PCI-E physical layer transmitter over the differential signal pair.

9. The apparatus of claim 8 wherein the logic comprises:

a ferrite and resistor in parallel with each signal line of the differential signal pair between the transmitter and receiver.

10. The Apparatus of claim 8, wherein the SAS/SATA physical layer receiver includes buffers capable of buffering the communications received from the PCI-E transmitter over the differential signal pair.

11. The Apparatus of claim 8, wherein the SAS/SATA physical layer receiver provides an interconnect extension from the differential signal pair to another differential signal pair for carrying the communications received from the PCI-E physical layer transmitter.

12. The Apparatus of claim 8, wherein the logic, by causing the differential signal pair to charge, enables the SAS/SATA physical layer receiver to perform link training with the PCI-E physical layer transmitter.

13. A method comprising the steps of:

providing a type one protocol device physical layer transmitter that performs a physical layer detection function to detect type one protocol device physical layer receivers attached via an interconnect, said detection function operating such that in response to a signal sent from the physical layer detection function, physical layer receivers having type one physical layer termination cause the interconnect to charge so physical layer receivers having type two physical layer termination appear as an open circuit to said physical layer detection function;

providing a type two protocol device physical layer receiver having type two physical layer termination, the type two protocol device physical layer receiver being connected to the type one protocol device physical layer transmitter by at least one differential signal pair; and

coupling logic to the at least one differential signal pair between the type two protocol device physical layer receiver and the type one protocol device physical layer transmitter, the logic functional to cause the type one protocol device transmitter physical layer detection function to detect the type two protocol device physical layer receiver as a type one protocol device physical layer receiver by causing the at least one differential signal pair to charge to indicate that the type two protocol device physical layer receiver is a valid type one protocol device physical layer receiver and to enable the type two protocol device physical layer receiver to functionally receive type one protocol communications directly from the type one protocol device physical layer transmitter over the at least one differential signal pair.

14. The method of claim 13 wherein the type one protocol device physical layer transmitter is a PCI-E device physical layer transmitter.

15. The method of claim 14 wherein the type two protocol device physical layer receiver is a SAS/SATA device physical layer receiver.

16. The method of claim 15 wherein the type one protocol device physical layer transmitter and type two protocol device physical layer receiver are differential, and wherein the step of coupling logic further comprises the step of coupling logic for each signal line of the at least one differential signal pair comprising:

a ferrite and resistor in parallel.

17. The method of claim 13, further comprising buffering, by the type two protocol device physical layer receiver, signals received from the type one protocol device physical layer transmitter.

18. The method of claim 13, wherein extending, by the type two protocol device physical layer receiver, the interconnect to another interconnect for carrying the signals received from the type one protocol device physical layer transmitter.

19. The method of claim 13, further comprising enabling, by the charging of the at least one differential signal pair, link training between the type two protocol device physical layer receiver and the type one protocol device physical layer transmitter.