Flash memory device for allocating physical blocks to logical blocks based on an erase count

• US 8,447,915 B2
• Filed: 07/23/2009
• Issued: 05/21/2013
• Est. Priority Date: 07/23/2009
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Araki, Akihiko, Sugimoto, Sadahiro, Yamamoto, Masayuki, Yamamoto, Akira
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US12/668,755
• Publication Number:
  US 20110191521A1
• Time in Patent Office: 1,398 Days
• Field of Search: 711/103, 711/E12.008, 711/164, 711/156, 365/185.3, 365/185.33
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

A controller in a flash memory device manages erase count of each physical block and manages the erase frequency of each logical block. The controller allocates a logical block whose erase frequency is high to one or more physical blocks whose erase count is low.

Claims

1. A flash memory device comprising:

multiple flash memory chips including multiple physical blocks, each of the multiple physical blocks being an erase unit and including multiple physical pages, each of the multiple physical pages being a read/write unit; and

a controller that allocates a physical block from among the multiple physical blocks to a certain logical block among multiple logical blocks that constitute a logical block space to a computer,

wherein the controller;

(A) manages an erase count for each physical block and the erase frequency of each logical block, and when the erase processing is carried out for the one or more physical blocks, updates the erase count for those one or more physical blocks, and the erase frequency of the logical block allocated to the physical blocks; and

(B) allocates a physical block whose erase count is lower than a threshold to logical blocks whose erase frequency is greater than or equal to an erase frequency threshold,

wherein the controller executes reclamation processing when the size of a free space of one or more target blocks is smaller than the size of data that is a write command target,

wherein the one or more target blocks are one or more physical blocks to which the write destination logical block is allocated,

wherein the write destination logical block is a logical block having an address specified in a write command from the host, and in the reclamation processing, the controller;

(a) determines whether the erase frequency of the write destination logical block is greater than or equal to the erase frequency threshold, and whether the erase count of the target block is greater than or equal to an erase count threshold;

(b) if the result of the determination in (a) is positive, selects one or more free blocks as an allocation destination of the write destination logical block from among multiple free blocks that are physical blocks having an erase count that is lower than the erase count threshold, and if the result of the determination in (a) is negative, the controller selects, from among the multiple free blocks, a free block having erase count corresponding to a level of erase count which is the same as, or as close as possible to, a level of erase count to which erase count of the target block belongs;

(c) copies the latest data for each storage area within the target block to the free block selected in (b), and allocates the write destination logical block to the copy destination free block;

(d) carries out the erase processing for the target block, and in accordance with this operation, updates erase count of the target block and updates the erase frequency of the write destination logical block;

(e) manages the target block as a free block;

(f) increases erase count threshold if erase count threshold is equal to or less than an average value of erase count of the multiple physical blocks; and

(g) updates the erase frequency threshold to the average value of the erase frequencies of the multiple logical blocks.

2. The flash memory device according to claim 1,

wherein the multiple flash memory chips are included in multiple flash drives,

wherein one or more RAID groups are configured based on the multiple flash drives, wherein the controller manages a logical unit, receives access requests from the host that specifies the logical unit, identifies the storage area for the logical unit based on the address specified in the access request, and issues an access command to the flash drives configuring the RAID group which is the basis of the identified storage area, and

wherein the controller carries out the reclamation processing for each of the multiple flash drives.

3. The flash memory device according to claim 1,

wherein the controller stores cold block management information, which is information associated with a physical block allocated to a logical block whose erase frequency is less than the erase frequency threshold, and hot block management information, which is information associated with a physical block allocated to a logical block whose erase frequency is greater than or equal to the erase frequency threshold,

wherein prior to the processing in (g), if the erase frequency of the write destination logical block is greater than or equal to the erase frequency threshold, the controller associates the copy destination physical block in (c) with the hot block information, and if the erase frequency of the write destination logical block is less than the erase frequency threshold, the controller associates the copy destination physical block in (c) with the cold block information, and

wherein in (g), the controller associates the physical block allocated to each logical block whose erase frequency is less than the erase frequency threshold after updating with the cold block information, and associates the physical block allocated to each logical block whose erase frequency is greater than or equal to the erase frequency threshold after updating with the hot block information.

4. A storage system, wherein in the flash memory device according to claim 1,

wherein the controller manages information representing a guarantee period of the flash memory device,

wherein the controller updates the erase frequency threshold to an allowable erase frequency instead of the average value of the erase frequencies of the multiple logical blocks, and

wherein the allowable erase frequency is a value obtained by dividing an upper limit of erase count of the physical block by the guarantee period.

5. The flash memory device according to claim 1, wherein the erase frequency threshold is a value based on the statistics of the erase frequencies of the multiple logical blocks.

6. The flash memory device according to claim 1, wherein the erase frequency threshold is a value obtained by dividing an upper limit of erase count of the physical block by the guarantee period of the flash memory device.

7. The flash memory device according to claim 1,

wherein the multiple flash memory chips are included in multiple flash drives, one or more RAID groups are configured based on the multiple flash drives, and

wherein the controller manages a logical unit, receives access requests from the host that specifies the logical unit, identifies the storage area for the logical unit based on the address specified in the access request , and issues an access command to the flash drives configuring the RAID group which is the basis of the identified storage area.

8. A flash device comprising:

multiple flash memory chips including multiple physical blocks, each of the multiple physical blocks being an erase unit and including multiple physical pages, each of the multiple physical pages being a read/write unit; and

a controller that allocates a physical block from among the multiple physical blocks to a certain logical block among multiple logical blocks that constitute a logical block space to a computer,

wherein the controller;

(A) manages an erase count for each physical block and the erase frequency of each logical block, and when the erase processing is carried out for the one or more physical blocks, updates the erase count for those one or more physical blocks, and the erase frequency of the logical block allocated to the physical blocks; and

(B) allocates a physical block whose erase count is lower than a threshold to logical blocks whose erase frequency is greater than or equal to an erase frequency threshold,

wherein (B), the controller;

(B1) determines whether the erase frequency of the target logical block allocated to one or more target physical blocks is greater than or equal to the erase frequency threshold, and whether erase count of the target physical block is greater than or equal to an erase count threshold;

(B2) if the result of the determination in (B1) is positive, selects one or more free blocks whose erase count is lower than erase count threshold as an allocation destination of the target logical block, from among multiple free blocks that are physical blocks that can be the allocation destination of the logical block, and if the determination result in (B1) is negative, the controller selects, from among the multiple free blocks, a free block having erase count corresponding to a level of erase count which is the same as, or as close as possible to, a level of erase count to which erase count of the target block belongs; and

(B3) copies the latest data for each storage area within the target physical block to the free block selected in (B2), and allocates the target logical block to the copy destination free block.

9. The flash memory device according to claim 8,

wherein the controller executes reclamation processing when the size of a free space of one or more target blocks is smaller than the size of data that is a write command target,

wherein the one or more target blocks are one or more physical blocks to which the write destination logical block is allocated,

wherein the write destination logical block is a logical block having an address specified in a write command from the host, and

wherein in the reclamation processing, the controller executes (B1).